Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—Low Pin Count (LPC) Controller—C2000 Product Family
Architectural Overview
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
504
Order Number: 330061-002US
24.2.2.2
Boot BIOS Strap
The SoC can boot from BIOS that resides in Flash, in either the SPI Flash or the LPC
(FWH) Flash. There are Boot BIOS System Straps which must be configured to indicate
which interface to utilize for BIOS Boot.
Note:
The default value of “11b” (Boot from SPI) is set from BIOS soft straps.
24.2.2.3
LPC Cycle Decoding
Depending on the platform design, the following configuration registers must be
programmed properly by System BIOS for SoC to positively decode LPC cycles targeted
to the FWH on the LPC:
• Boot BIOS Straps set to “00b” to insure BIOS cycles are routed to LPC
• FWH ID Select registers located at [B:0, D:31, F:0] + 50h are configured
• Enable Bits in the BIOS Decode Enable (BDE) Register are configured
• FWH ID Select registers located at [B:0, D:31, F:0] + 50h are configured
• Enable Bits in the BIOS Decode Enable (BDE) Register are configured
24.2.2.4
LPC Notes
All cycles that are not decoded internally, and are not targeted for LPC (i.e.,
configuration cycles, IO cycles above 64KB and memory cycles above 16MB), will be
sent to LPC with FRAME# not asserted. This aids external debug tools.
Table 24-4. BBS Configurations
Description
00
Boot from LPC
11
Boot from SPI
01 or 10
Reserved
Table 24-5. Signal Pin Configurations
SoC Signal Pin
Name
Functional
Options and
Occurrences
SoC Signal
Represented by
Pin
Direction
(I/O)
Internal
Pull-up (PU)
or
Pull-down
(PD)
Power Rail
FLEX_CLK_SE0
Strap Sampling
0 = LPC / 1 = SPI
1
20K PU
V3P3S
As BIOS Starts
FLEX_CLK_SE0
0
None
V3P3S
SC_USE_SEL = 1
GPIOS_19
Set by SW
TBD
V3P3S