Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

513

• Edge-Detect (E-Detect) capability for predefined pads

— Wake-up event input pin capability for GPIO_SUS[3:0] and GPIO_SUS[7:6]
— E-event capture capability for GPIOS[7:0]

• Alternate functions for GPIOs to reduce the SoC pin count
• Filter (de-glitch) capabilities for predefined pads

— GPIO_SUS[3:0] and GPIO_SUS[9:8]
— GPIOS[7:0] and GPIOS[18:15]

• Customer GPIO interface, located in the I/O addressing space
• Electrical parameters controlled by the software via registers in the memory space
• Consolidate all DFx and functional muxing at one entity

If their native functions are not used, a number of the SoC signal pins can be 

programmed to be used as Customer General-Purpose IO pins. Typically this 

programming is performed by the BIOS. The software uses a number of GPIO 

configuration registers to make this choice.

Each Customer GPIO port is implemented as dual-read/write registers with its own 

dedicated storage. From the CPU standpoint, a write value is stored in the write 

register, while the read value comes from the GPIO read register.