Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—General-Purpose I/O (GPIO)—C2000 Product Family
Architectural Overview
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
514
Order Number: 330061-002US
25.3.1
Choosing the Native Signal Mode or Customer GPIO Mode
The 31 GPIO ports in the core well are handled separately from the 28 GPIO ports in
the SUS well.
• Six 32-bit GPIO control/access registers (see
) are associated with the
31 Customer GPIO ports in the core well. Each bit represents a Customer GPIO
register in the core well (bit 0 = GPIOS0, bit 1 = GPIOS1, etc.). Bit 31 is reserved.
• Seven 32-bit GPIO control/access registers (see
) are associated with
the 28 Customer GPIO ports in the SUS well. Each bit represents a Customer GPIO
register in the SUS well (bit 0 = GPIO_SUS0, bit 1 = GPIO_SUS1, etc.). Bits 28
through 31 are reserved.
Note:
Bit 0 of each register corresponds to GPIOS0. Bit 1 corresponds to GPIOS1, and so on.
Note:
Table 25-2. GPIO Core Control/Access Registers in I/O Space
Name
Bits Used of the
32-Bit Register
Description
00h
SC_USE_SEL
31 (one per GPIO)
Use Select
04h
SC_IO_SEL
31 (one per GPIO)
Input Output Select
08h
SC_GP_LVL
31 (one per GPIO)
GPIO Level
0Ch
SC_TPE
31 (one per GPIO)
Trigger Positive Edge Enable
10h
SC_TNE
31 (one per GPIO)
Trigger Negative Edge Enable
14h
SC_TS
31 (one per GPIO)
Trigger Status
Table 25-3. GPIO SUS Control/Access Registers in I/O Space
Name
Bits Used of the
32-Bit Register
Description
80h
SUS_USE_SEL
28 (one per GPIO)
Use Select
84h
SUS_IO_SEL
28 (one per GPIO)
Input Output Select
88h
SUS_GP_LVL
28 (one per GPIO)
GPIO Level
8Ch
SUS_TPE
28 (one per GPIO)
Trigger Positive Edge Enable
90h
SUS_TNE
28 (one per GPIO)
Trigger Negative Edge Enable
94h
SUS_TS
28 (one per GPIO)
Trigger Status
98h
SUS_WAKE_EN
28 (one per GPIO)
Wake Enable