Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

515

• Use as a Customer GPIO

— When the bit corresponding to a particular Customer GPIO pin is set to a 1 in 

the USE_SEL register, the pin is available as a general-purpose IO.

• Use as a Native Signal

— When the bit corresponding to a particular Customer GPIO pin is set to a 0 in 

the USE_SEL register, the pin is used in its native signal mode. Most pins that 

can be programmed as Customer GPIOs have only one native signal as an 

alternative. A small number of Customer GPIOs in the Suspend (SUS) power 

well have two possible native signals as an alternative.

The ball/pin signal I/O buffers are set as 3.3V buffers and cannot be changed.

For additional details reference 

.

Because most of the GPIO pins are shared with the other SoC functional signals, the 

board designer must pay attention to the way these pins are configured by the SoC 

after reset and before the software sets the GPIO USE_SEL bit to 1.

The safest method to avoid circuit contention on the board is to configure a GPIO pin to 

have the same input/output assignment as the SoC native signal for that pin. The 

internal termination resistors must also be taken into account. Refer to 

 and 

 for the pin signal 

direction and internal termination of the shared signals. Also, see 

.

The GPIO pins that are also hard-strap pins need this special attention too. When a pin 

is sampled for the strap value, the SoC treats the pin as an input regardless of its 

native-signal direction. During this strap-sampling time, a special internal Pull-Up (PU) 

or Pull-Down (PD) resistor may be tied to the pin regardless of the internal termination 

of the native function.