Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

550

Order Number: 330061-002US

The PIC interrupt sequence involves 3 bits, from the IRR, ISR, and IMR, for each 

interrupt level. These bits are used to determine the interrupt vector returned and the 

status of any other pending interrupts. 

 defines the IRR, ISR, and IMR.

The processor generates an interrupt acknowledge cycle that is translated into a 

interrupt acknowledge cycle to the SoC. The PIC translates this command into two 

internal INTA# pulses expected by the 8259 controllers. The PIC uses the first internal 

INTA# pulse to freeze the state of the interrupts for priority resolution. On the second 

INTA# pulse, the master or slave sends the interrupt vector to the processor with the 

acknowledged interrupt code. This code is based on the ICW2.IVBA bits, combined with 

the ICW2.IRL bits representing the interrupt within that controller.

References to the ICWx and OCWx registers in 

 are relevant to both the 

master and slave 8259 controllers.

IRR

This bit is set on a low-to-high transition of the interrupt line in the 

edge mode and by an active high level in the level mode.

ISR

 This bit is set, and the corresponding IRR bit cleared, when an 

interrupt acknowledge cycle is seen, and the vector returned is for that interrupt.

IMR

This bit determines whether an interrupt is masked. Masked interrupts 

do not generate INTR.

IRQ7,15

ICW2.IVBA

111

IRQ6,14

110

IRQ5,13

101

IRQ4,12

100

IRQ3,11

011

IRQ2,10

010

IRQ1,9

001

IRQ0,8

000