Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

552

Order Number: 330061-002US

Before an operation begins, each 8259 must be initialized. In the SoC, this is a 4-byte 

sequence. The four initialization command words are referred to by their acronyms: 

ICW1, ICW2, ICW3, and ICW4.

The base address for each 8259 initialization command word is a fixed location in the 

I/O space: 20h for the master controller and A0h for the slave controller.

A write to the master or slave controller base address with data bit 4 equal to 1 is 

interpreted as a write to ICW1. Upon sensing this write, the PIC expects three more 

byte writes to 21h for the master controller or A1h for the slave controller to complete 

the ICW sequence.

A write to ICW1 starts the initialization sequence during which the following 

automatically occurs:

1. Following initialization, an Interrupt Request (IRQ) input must make a low-to-high 

transition to generate an interrupt.

2. The Interrupt Mask Register is cleared.
3. IRQ7 input is assigned priority 7.
4. The slave mode address is set to 7.
5. Special mask mode is cleared, and the status read is set to IRR.

The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the 

interrupt vector that are released during an interrupt acknowledge. A different base is 

selected for each interrupt controller.

The third write in the sequence (ICW3) has a different meaning for each controller.

• For the slave controller, ICW3 is the slave identification code used during an 

interrupt acknowledge cycle. On interrupt acknowledge cycles, the master 

controller broadcasts a code to the slave controller if the cascaded interrupt won 

arbitration on the master controller. The slave controller compares this 

identification code to the value stored in its ICW3, and if it matches, the slave 

controller assumes responsibility for broadcasting the interrupt vector.

The final write in the sequence (ICW4) must be programmed for both controllers. At 

least, ICW4.MM must be set to a 1 to indicate the controllers are operating in an Intel

®

 

architecture system.