Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

551

1. One or more of the Interrupt Request lines (IRQ) are raised high in the edge mode 

or seen high in the level mode, setting the corresponding IRR bit.

2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.
3. The processor acknowledges the INTR and responds with an interrupt acknowledge 

cycle.

4. When observing the special cycle, the SoC converts it into the two cycles that the 

internal 8259 pair responds. Each cycle appears as an interrupt acknowledge pulse 

on the internal INTA# pin of the cascaded interrupt controllers.

5. When receiving the first internally generated INTA# pulse, the highest priority ISR 

bit is set and the corresponding IRR bit is reset. On the trailing edge of the first 

pulse, a slave identification code is broadcast by the master to the slave on a 

private, internal 3-bit wide bus. The slave controller uses these bits to determine if 

it must respond with an interrupt vector during the second INTA# pulse.

6. When receiving the second internally generated INTA# pulse, the PIC returns the 

interrupt vector. If no interrupt request is present because the request was too 

short in duration, the PIC returns vector 7 from the master controller.

7. This completes the interrupt cycle. In AEOI mode, the ISR bit is reset at the end of 

the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate 

EOI command is issued at the end of the interrupt subroutine.