Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

562

Order Number: 330061-002US

The I/O APIC has no external signal pins.

• 24 interrupt lines

— IRQ0-23

• Edge- or level-trigger mode per interrupt
• Active low or high polarity per interrupt
• MSIs target the specific processor core
• Established APIC programming model

There are 24 I/O Redirection Table Entry registers. Each register is a dedicated entry 

for each interrupt input signal. For information about interrupts routed to the I/O APIC, 

see 

Unlike IRQ pins of the 8259A, the notion of interrupt priority is completely unrelated to 

the position of the physical interrupt input signal on the I/O APIC. Instead, the software 

determines the vector (and therefore the priority) for each corresponding interrupt 

input signal. For each interrupt signal, the operating system also specifies the signal 

polarity (low active or high active), whether the interrupt is signaled as edges or levels, 

as well as the destination and delivery mode of the interrupt.

The information in the redirection table translates the corresponding interrupt pin 

information into an inter-APIC message.

The software does not attempt to write to reserved registers. Reserved registers may 

return non-zero values when read.

See 

 for descriptions of these I/O APIC internal registers.

00h

ID

Identification. The software must program an APIC 

Identification (AID) value before using the APIC.

01h

VS

Version. A read-only register identifying it as IOxAPIC 

with 24 I/O interrupts.

02h through 0Fh

-

Reserved

10h and 11h

RTE0

Redirection Table Entry 0

12h and 13h

RTE1

Redirection Table Entry 1

…

…

…

3Eh and 3Fh

RTE23

Redirection Table Entry 23

40h through FFh

-

Reserved