Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

563

The I/O APIC has a 32-bit APIC Identification register and a 32-bit Version register.

The SoC I/O APIC accommodates up to 24 I/O interrupts. It provides a 64-bit I/O-

Interrupt Redirection register for each. The Redirection register contains:

• An 8-bit Destination ID (DID) of the local APIC for the interrupt.
• An 8-bit Extended Destination ID (DID) of the local APIC for the interrupt.
• 4 bits to indicate the mask, trigger mode, remote IRR (for trigger mode), and 

polarity for the interrupt.

• 5 bits for the interrupt delivery mode and delivery status.
• 8 bits containing the interrupt Vector (VCT) with values of 10h through FEh.

The MSIs generated by the I/O APIC are sent as 32-bit memory writes to the local 

APIC. The Destination ID (DID) and Extended Destination ID (EDID) are used to target 

a specific processor core local APIC.

The I/O APIC internal registers are accessed indirectly. They are accessed using three 

registers in the memory space. The three registers have fixed memory addresses as 

shown in 

• The 32-bit APIC Identification register is accessed through this mechanism.
• The 32-bit Version register is accessed through this mechanism.
• The twenty-four, 64-bit Redirection Table Entries (RTE0 through RTE23) are only 

• Some of the 256 registers are reserved. See 

The registers that appear in the WDW register are described in the following sections 

and tables.

0xFEC00000

00h

IOAPIC_IDX

0xFEC00010

0000_0000h

IOAPIC_WDW

0xFEC00040

0000_0000h

IOAPIC_EOI