Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—I/O Advanced APIC (I/O APIC)—C2000 Product Family
Architectural Overview
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
564
Order Number: 330061-002US
30.3.3.1
Identification (ID) Register
The 32-bit Identification (ID) register is accessed at offset 00h.
30.3.3.2
Version (VS) Register
The 32-bit Version (VS) register is accessed at offset 01h.
Table 30-3. Identification (ID) Register
Bits
Type
Reset
Description
31:28
RO
0
Reserved
27:24
RW
0
APIC Identification (AID):
Software must program this value before using the
APIC.
23:16
RO
0
Reserved
15
RW
0
Scratchpad
14
RW
0
Reserved. Writing to this bit has no effect.
13:0
RO
0
Reserved
Table 30-4. Version (VS) Register
Bits
Type
Reset
Description
31:24
RO
0
Reserved
23:16
RO
17h
Maximum Redirection Entries (MRE):
This is the entry number (0 being the
lowest entry) of the highest entry in the redirection table. This field is hard-wired to
17h to indicate 24 interrupts.
15
RO
0
Pin Assertion Register Supported (PRQ):
The IOxAPIC does not implement the
Pin Assertion Register.
14:8
RO
0
Reserved
7:0
RO
20h
Version (VS):
Identifies the implementation version as IOxAPIC.