Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4383
31.5.2
HSFSTS (Hardware_Sequencing_Flash_Status_bios)—Offset 4h
Hardware sequencing flash status Note: If operating in Non-Descriptor mode, the
Software Sequencing Flash Status register must be used.
Access Method
Default: 0000h
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Hardware_Sequencing_Flash_Status_bios:
SPI_BASE_ADDRESS Type:
PCI Configuration Register (Size: 32
bits)
SPI_BASE_ADDRESS Reference:
SPI_BASE_ADDRESS Reference:
[B:0, D:31, F:0] + 54h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FL
OC
KDN
FDV
FDO
P
S
S
RS
VD0
SC
IP
BE
RA
SE
AE
L
FCERR
FD
ONE
Bit
Range
Default &
Access
Description
15
0b
RW/L
Flash Configuration Lock-Down (FLOCKDN):
When set to 1, those Flash Program
Registers that are locked down by this FLOCKDN bit cannot be written. Once set to 1,
this bit can only be cleared by a hardware reset.
14
0b
RO
Flash Descriptor Valid (FDV):
This bit is set to a 1 if the Flash Controller read the
correct Flash Descriptor Signature. If the Flash Descriptor Valid bit is not 1 , software
cannot use the Hardware Sequencing registers, but must use the software sequencing
registers. Any attempt to use the Hardware Sequencing registers will result in the
FCERR bit being set.
13
0b
RO
Flash Descriptor Override Pin-Strap Status (FDOPSS):
This register reflects the
value the Flash Descriptor Override Pin-Strap. '1': No override '0': The Flash Descriptor
Overide strap is set
12:6
0b
RO
RSVD0:
Reserved
5
0b
RO
SPI Cycle In Progress (SCIP):
Hardware sets this bit when software sets the Flash
Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains
set until the cycle completes on the SPI interface. Hardware automatically sets and
clears this bit so that software can determine when read data is valid and/or when it is
safe to begin programming the next command. Software must only program the next
command when this bit is 0.
4:3
00b
RO
Block/Sector Erase Size (BERASE):
This field identifies the erasable sector size for
all Flash components. Valid Bit Settings: 00 : 256 Byte 01 : 4K Byte 10 : 8K Byte 11 :
64K Byte If the FLA ( FPBA then this field reflects the value in the LVSCC.LBES register.
If the FLA )= FPBA then this field reflects the value in the UVSCC.UBES register.
2
0b
RW/1C
Access Error Log (AEL):
Hardware sets this bit to a 1 when a direct read was made by
BIOS that violated the security restrictions. Or , when a SB transaction to read/write
one of the BIOS registers was accepted with bad SAI - see security table. This bit has no
affect on indirect accesses. This bit is cleared by software writing a 1.
1
0b
RW/1C
Flash Cycle Error (FCERR):
Hardware sets this bit to 1 when an program register
access is blocked to the FLASH due to one of the protection policies or when any of the
programmed cycle registers is written while a programmed access is already in
progress. This bit remains asserted until cleared by software writing a 1 or until
hardware reset occures. Software must clear this bit before setting the FLASH Cycle GO
bit in this register.