Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
4384
Datasheet
31.5.3
HSFCTL (Hardware_Sequencing_Flash_Control_bios)—Offset
6h
Hardware sequencing flash control.
Access Method
Default: 0000h
0
0b
RW/1C
Flash Cycle Done (FDONE):
The SPI controller sets this bit to 1 when the SPI Cycle
completes after software previously set the FGO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset. When this bit is set and the SPI SMI#
Enable bit is set, an internal signal is asserted to the SMI# generation block. Software
must make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new
programmed access.
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Hardware_Sequencing_Flash_Control_bios:
SPI_BASE_ADDRESS Type:
PCI Configuration Register (Size: 32
bits)
SPI_BASE_ADDRESS Reference:
SPI_BASE_ADDRESS Reference:
[B:0, D:31, F:0] + 54h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FSMIE
RSV
D
0
FDBC
RRWSP
FCYCLE
FG
O
Bit
Range
Default &
Access
Description
15
0b
RW
Flash SPI SMI# Enable (FSMIE):
When set to 1, the SPI asserts an SMI# request
whenever the Flash Cycle Done bit is 1.
14
0b
RO
RSVD0:
Reserved
13:8
00h
RW
Flash Data Byte Count (FDBC):
This field specifies the number of bytes to shift in or
out during the data portion of the SPI cycle. The contents of this register are 0s based
with 0b reprenting 1 byte and 111111b representing 64 bytes. The number of bytes
transferred is the value of this field plus 1. This field is ignored for the Block Erase
command.
7:3
00h
RW
Reserved RW Scratch Pad (RRWSP):
Reserved: Scratch Pad bits that are R/W to be
used during ECO
2:1
00b
RW
FLASH Cycle (FCYCLE):
This field defines the Flash SPI cycle type generated to the
FLASH when the FGO bit is set as defined below: 00 Read (1 up to 64 bytes by setting
FDBC) 01 Reserved 10 Write (1 up to 64 bytes by setting FDBC) 11 Block Erase
Implementation Note: if reserved 2'b01 is programmed to this field, flash controller will
handle it as if it is 00 (Read)
0
0b
RW/SE
Flash Cycle Go (FGO):
A write to this register with a 1 in this bit initiates a request to
the Flash SPI Arbiter to start a cycle. This register is cleared by hardware when the cycle
is granted by the SPI arbiter to run the cycle on the SPI bus. When the cycle is
complete, the FDONE bit is set. Software is forbidden to write to any register in the
HSFLCTL register between the FGO bit getting set and the FDONE bit being cleared. Any
attempt to violate this rule will be ignored by hardware. Hardware allows other bits in
this register to be programmed for the same transaction when writing this bit to 1. This
saves an additional memory write. This bit always returns 0 on reads.