Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
PCU – System Management Bus (SMBus)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4435
33.2.2
Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the
PCU_SMB_DATA line low to signal a start condition. The SoC continuously monitors the
PCU_SMB_DATA line. When the SoC is attempting to drive the bus to a 1 by letting go
of the PCU_SMB_DATA line, and it samples PCU_SMB_DATA low, then some other
master is driving the bus and the SoC will stop transferring data.
PCU_SMB_DATA line low to signal a start condition. The SoC continuously monitors the
PCU_SMB_DATA line. When the SoC is attempting to drive the bus to a 1 by letting go
of the PCU_SMB_DATA line, and it samples PCU_SMB_DATA low, then some other
master is driving the bus and the SoC will stop transferring data.
If the SoC sees that it has lost arbitration, the condition is called a collision. The SoC
will set SMB_Mem_HSTS.BERR, and if enabled, generate an interrupt or SMI#. The
processor is responsible for restarting the transaction.
will set SMB_Mem_HSTS.BERR, and if enabled, generate an interrupt or SMI#. The
processor is responsible for restarting the transaction.
The SoC, as a SMBus master, drives the clock. When the SoC is sending address or
command or data bytes on writes, it drives data relative to the clock it is also driving. It
will not start toggling the clock until the start or stop condition meets proper setup and
hold time. The SoC will also ensure minimum time between SMBus transactions as a
master.
command or data bytes on writes, it drives data relative to the clock it is also driving. It
will not start toggling the clock until the start or stop condition meets proper setup and
hold time. The SoC will also ensure minimum time between SMBus transactions as a
master.
33.2.3
Bus Timing
33.2.3.1
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the SoC as
an SMBus master would like. They have the capability of stretching the low time of the
clock. When the SoC attempts to release the clock (allowing the clock to go high), the
clock will remain low for an extended period of time.
an SMBus master would like. They have the capability of stretching the low time of the
clock. When the SoC attempts to release the clock (allowing the clock to go high), the
clock will remain low for an extended period of time.
The SoC monitors the SMBus clock line after it releases the bus to determine whether
to enable the counter for the high time of the clock. While the bus is still low, the high
time counter must not be enabled. Similarly, the low period of the clock can be
stretched by an SMBus master if it is not ready to send or receive data.
to enable the counter for the high time of the clock. While the bus is still low, the high
time counter must not be enabled. Similarly, the low period of the clock can be
stretched by an SMBus master if it is not ready to send or receive data.
33.2.3.2
Bus Time Out (SoC as SMBus Master)
If there is an error in the transaction, such that an SMBus device does not signal an
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. The SoC will discard the cycle and set the SMB_Mem_HSTS.DEVERR bit.
The time out minimum is 25 ms (800 RTC clocks). The time-out counter inside the SoC
will start after the last bit of data is transferred by the SoC and it is waiting for a
response.
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. The SoC will discard the cycle and set the SMB_Mem_HSTS.DEVERR bit.
The time out minimum is 25 ms (800 RTC clocks). The time-out counter inside the SoC
will start after the last bit of data is transferred by the SoC and it is waiting for a
response.
The 25-ms time-out counter will not count under the following conditions:
1. The SMB_Mem_HSTS.BYTE_DONE_STS bit is set
2. The TCO_STS.SECOND_TO_STS bit is not set (this indicates that the system has not
locked up).
locked up).