Intel E3845 FH8065301487715 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

4436

Datasheet

The SoC SMBus controller uses INTB as its virtual interrupt wire. However, the system 
can alternatively be set up to generate SMI# instead of an interrupt, by setting the 
SMB_Config_HCFG.SMI_EN bit.

Below tables specify how the various enable bits in the SMBus function control the 
generation of the interrupt and Host SMI internal signals. The rows in the tables are 
additive, which means that if more than one row is true for a particular scenario then 
the Results for all of the activated rows will occur.

PCU_SMB_ALERT# is multiplexed with GPIO_S0_SC[53]. When enabled and the signal 
is asserted, the SoC can generate an interrupt or an SMI#.

PCU_SMB_ALERT# 
asserted low 
(always reported 
in SMB_Mem_ 

HSTS.SMBALERT)

X

1

0

Slave  SMI# 
generated 

(SMBUS_SMI_S
TS)

1

0

0

Interrupt 
generated

Any combination of 
SMB_Mem_HSTS. 

FAILED, 
SMB_Mem_HSTS. 

BERR, 
SMB_Mem_HSTS. 

DEVERR, 
SMB_Mem_HSTS. 

INTR asserted

0

X

None

1

0

Interrupt generated

1

1

Host  SMI#  generated

0

X

0

None

1

0

X

Interrupt generated

1

1

X

Slave SMI# generated 
(SMBUS_SMI_STS)