Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Datasheet
1045
PCU – Serial Peripheral Interface (SPI)
Note:
All SPI signals are tri-stated with 20k ohm internal weak pull-up until
PMC_CORE_PWROK is asserted.
PMC_CORE_PWROK is asserted.
21.2
Features
The SPI controller supports up to two SPI Flash devices using two separate chip select
pins. Each SPI Flash device can be up to 16 MB. The processor SPI interface supports
20 MHz, 33 MHz and 50 MHz SPI Flash devices. No other types of SPI devices are
supported.
pins. Each SPI Flash device can be up to 16 MB. The processor SPI interface supports
20 MHz, 33 MHz and 50 MHz SPI Flash devices. No other types of SPI devices are
supported.
Communication on the SPI bus is done with a Master – Slave protocol. The Slave is
connected to the processor and is implemented as a tri-state bus.
connected to the processor and is implemented as a tri-state bus.
Note:
When GCS.BBS = 00b, LPC is selected as the location for BIOS. The SPI Flash may still
contain data and firmware for other processor functionality.
contain data and firmware for other processor functionality.
Note:
When GCS.BBS =11b and a SPI device is detected by the processor, LPC based BIOS
Flash is disabled.
Flash is disabled.
Table 153. SPI Signals
Signal Name
Direction/
Type
Description
PCU_SPI_CLK
O
CMOS1.8
SPI Clock: When the bus is idle, the owner will drive the clock signal
low.
PCU_SPI_CS[0]#
O
CMOS1.8
SPI Chip Select 0: Used as the SPI bus request signal for the first SPI
Flash device.
PCU_SPI_CS[1]#
O
CMOS1.8
SPI Chip Select 1: Used as the SPI bus request signal for the second
SPI Flash devices.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
PCU_SPI_MISO
I
CMOS1.8
SPI Master IN Slave OUT: Data input pin for the processor.
PCU_SPI_MOSI
I/O
CMOS1.8
SPI Master OUT Slave IN: Data output pin for the processor.
Operates as a second data input pin for the processor when in Single
Input, Dual Output Fast Read mode.