Intel N2820 FH8065301616603 Data Sheet

Product codes
FH8065301616603
Page of 1294
Datasheet
1047
PCU – Serial Peripheral Interface (SPI)
SPI Flash Regions
In Descriptor Mode the Flash is divided into five separate regions as shown in the 
following table.
Only masters can access the four regions: The processor core running BIOS code and 
the Trusted Execution Engine. The only required region is Region 0, the Flash 
Descriptor. Region 0 must be located in the first sector of Device 0. 
Flash Regions Sizes
SPI Flash space requirements differ by platform and configuration. 
the space needed in the Flash for each region.
21.2.3
Flash Descriptor
The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI 
Flash device is greater than 4 KB, the Flash descriptor will only use the first 4 KB of the 
first block. The Flash descriptor requires its own block at the bottom of memory (00h). 
The information stored in the Flash Descriptor can only be written during the 
manufacturing process as its read/write permissions must be set to Read only when the 
system containing the processor leaves the manufacturing floor. 
The Flash Descriptor is made up of eleven sections as indicated in the following figure. 
Table 154. SPI Flash Regions
Region
Content
0
Flash Descriptor
1
BIOS
2
Trusted Execution Engine
3
4
Platform Data
Table 155. Region Size Versus Erase Granularity of Flash Components
Region
Size with 4 KB 
Blocks
Size with 8 KB 
Blocks
Size with 64 KB Blocks
Descriptor
4 KB
8 KB
64 KB
BIOS
Varies by Platform
Varies by Platform
Varies by Platform
Trusted Execution Engine
TBD
TBD
TBD