Intel Atom Processor N270 AU80586GE025D Data Sheet

Datasheet  

 19 

The processor incorporates FSB low power enhancements: 

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BPRI# control for address and control input buffers 

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Dynamic Bus Parking 

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Dynamic On Die Termination disabling 

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Low VCCP (I/O termination voltage) 

The processor incorporates the DPWR# signal that controls the data bus input buffers 

on the processor. The DPWR# signal disables the buffers when not used and activates 

them only when data bus activity occurs, resulting in significant power savings with no 

performance impact. BPRI# control also allows the processor address and control 

input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking 

allows a reciprocal power reduction in chipset address and control input buffers when 

the processor de-asserts its BR0# pin. The on-die termination on the processor FSB 

buffers is disabled when the signals are driven low, resulting in additional power 

savings. The low I/O termination voltage is on a dedicated voltage plane independent 

of the core voltage, enabling low I/O switching power at all times. 

The processor has only one signaling mode, where the data and address buses and 

the strobe signals are operating in GTL mode. The reason to use GTL is to improve 

signal integrity. 

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