Oracle Vacuum Cleaner CPU-56T User Manual
Maps and Registers
System Configuration Registers
126
SPARC/CPU−56T
Address: 1FF.F160.0148
16
− 1FF.F160.014B
16
Table 38:
Timer Initial Control Registers
Bit
Name
Description
Default
Access
15..0
TIMER2 INIT
Initialization time of timer 2 in 16−bit mode
0000
0000
16
: Timer disabled
0001
16
: Timer run−out time is 10
µs
FFFF
16
: Timer run−out time is 655.35 ms
0000
16
r/w
31..16
TIMER1 INIT
Initialization time of timer 1 in 16−bit mode
0000
0000
16
: Timer disabled
0001
16
: Timer run−out time is 10
µs
FFFF
16
: Timer run−out time is 655.35 ms
0000
16
r/w
31..0
TIMER1 INIT
Initialization time of timer 1 in 32−bit mode
0000.0000
0000.0000
16
: Timer disabled
0000.0001
16
: Timer run−out time is 10
µs
FFFF.FFFF
16
: Timer run−out time is 42949.67295 s
00000000
16
r/w
Timer Counter Status Register
The following four registers are used to read the current timer value of both timers. The
32 bits are also distributed as big endian. To obtain the correct timer status when reading
all two or four bytes of a timer, an 16− or 32−bit access is necessary.
32 bits are also distributed as big endian. To obtain the correct timer status when reading
all two or four bytes of a timer, an 16− or 32−bit access is necessary.
a