Oracle Vacuum Cleaner CPU-56T User Manual
System Configuration Registers
Maps and Registers
SPARC/CPU−56T
127
Address: 1FF.F160.014C
16
− 1FF.F160.014F
16
Table 39:
Timer Counter Status Register
Bit
Name
Description
Default
Access
15..0
TIMER2 VALUE
Current value of timer 2 in 16−bit mode
0000
0000
16
: Timer 2 is not running.
0001
16
: Timer 2 will initialize again during the
next 10
µs.
7FFF
16
: Timer 2 needs 327.67 ms until next
initialization.
FFFF
FFFF
16
: Timer 2 needs 655.35 ms until next
initialization.
0000
16
r
31..16
TIMER1 VALUE
Current value of timer 1 in 16−bit mode
0000
0000
16
: Timer 1 is not running.
0001
16
: Timer 1 will initialize again during the
next 10
µs.
7FFF
16
: Timer 1 needs 327.67 ms until next
initialization.
FFFF
FFFF
16
: Timer 1 needs 655.35 ms until next
initialization.
0000
16
r
31..0
TIMER1 VALUE
Current value of timer 1 in 32−bit mode
0000.0000
0000.0000
16
: Timer 1 is not running.
a
0000.0001
16
: Timer 1 will initialize again during
the next 10
µs.
0000.7FFF
16
: Timer 1 needs 327.67 ms until next
initialization.
FFFF.FFFF
FFFF.FFFF
16
: Timer 1 needs 42949.67295 s until
next initialization.
0000.0000
16
r
Interrupt Registers
The interrupt registers are used to distribute all possible failures or status information to
the UPA interrupt concentrator (UIC). The registers are the central areas to enable the
interrupts and read back the status of a pending interrupt.
the UPA interrupt concentrator (UIC). The registers are the central areas to enable the
interrupts and read back the status of a pending interrupt.
a
Interrupts are cleared in different ways. The VME ACFAIL and SYSFAIL interrupts,
which detect the deassertion of the respective signals, are cleared by writing a 1 to the
respective bits in the Interrupt Pending Status Register. All other interrupts are cleared by
setting/clearing bits in their respective control registers. In order to clear the timer 1
interrupt, for example, the bit CLR_TIM1 in the Timer Clear Control register must be set
to 1.
which detect the deassertion of the respective signals, are cleared by writing a 1 to the
respective bits in the Interrupt Pending Status Register. All other interrupts are cleared by
setting/clearing bits in their respective control registers. In order to clear the timer 1
interrupt, for example, the bit CLR_TIM1 in the Timer Clear Control register must be set
to 1.
a
Interrupt Enable Control Register
This register is used to enable or disable the interrupt sources.