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Oracle Vacuum Cleaner CPU-56T User Manual

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Maps and Registers
System Configuration Registers
128
SPARC/CPU−56T
Address: 1FF.F160.0180
16
Table 40:
 Interrupt Enable Control Register
Bit
Name
Description
Default
Access
0
IE_WDT
Enables the watchdog timer interrupt.
a
0: Watchdog timer interrupt is disabled.
1: Watchdog timer interrupt is enabled.
0
2
r/w
1
Reserved
This bit is always zero.
0
2
r/w
2
IE_TEMP
Enables the Temperature Interrupt.
a
0: Temperature interrupt is disabled.
1: Temperature interrupt is enabled.
0
2
r/w
3
Reserved
This bit is always zero.
0
2
r/w
4
IE_TIMER1
Enables the timer 1 interrupt.
0: Timer 1 interrupt is disabled.
1: Timer 1 interrupt is enabled.
0
2
r/w
5
IE_TIMER2
Enables the timer 2 interrupt.
0: Timer 2 interrupt is disabled.
1: Timer 2 interrupt is enabled.
0
2
r/w
6
IE_ACFAIL
Enables the interrupt of the deassertion of the
VMEbus ACFAIL signal.
a
0: ACFAIL interrupt is disabled.
1: ACFAIL interrupt is enabled.
0
2
r/w
7
IE_SYSFAIL
Enables the interrupt of the deassertion of the
VMEbus SYSFAIL signal.
a
0: SYSFAIL interrupt is disabled.
1: SYSFAIL interrupt is enabled.
0
2
r/w
Interrupt Pending Status Register
This register reflects whether a certain interrupt is pending.
a
Address: 1FF.F160.0184
16
Table 41:
 Interrupt Pending Status Register
Bit
Name
Description
Default
Access
0
IP_WDT
Reflects if a Watchdog Timer Interrupt is pending
0: No Watchdog timer interrupt is pending.
1: The Watchdog timer interrupt is pending.
0
2
r
1
Reserved
Reserved
0
2
r