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Oracle Vacuum Cleaner CPU-56T User Manual

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Maps and Registers
System Configuration Registers
130
SPARC/CPU−56T
Bit
Access
Default
Description
Name
2
RST WD
Reflects whether the last reset has been generated
through a watchdog timer time−out condition
0: No watchdog timer reset has been triggered.
1: The watchdog timer reset has been triggered.
0
2
r
3
RST RTB
Reflects whether the last reset has been generated
through a push−button reset on the board
′s IOBP
0: No push−button reset from the CPU board
′s IOBP has
been triggered.
1: Push−button reset from the CPU board
′s IOBP has
been triggered.
0
2
r
4
RST VME
Reflects whether the last reset has been generated
through a VMEbus reset
0: No VMEbus reset has been triggered.
1: VMEbus reset has been triggered.
0
2
r
5
RST PMC
Reflects wheather the last reset has been generated
through a PMC module
0: No PMC reset has been triggered.
a
1: PMC reset has been triggered.
0
2
r
7..6
0
Reserved
00
2
r
Board Status Registers
The Board Status registers are used to identify the current configuration of the board. The
switch settings can be read from two registers.
Switch 1 and 2 Status Register
This register is used to read the switch settings of switches 1 and 2.
a
Address: 1FF.F160.01E0
16
a
Table 43:
 Switch 1 and 2 StatusRegister
Bit
Name
Switch Setting/Functionality
Default
Access
0
SW1−1
Flash memory write protection
0: ON (Flash memory writing enabled)
1: OFF (Flash memory writing disabled)
1
2
r
1
SW1−2
Boot device selection
0: ON (Boot from Flash memory)
1: OFF (Boot from PLCC PROM)
1
2
r
2
SW1−3
Watchdog enabling
0: ON (Watchdog enabled)
1: OFF (Watchdog disabled)
1
2
r