Oracle Vacuum Cleaner CPU-56T User Manual
System Configuration Registers
Maps and Registers
SPARC/CPU−56T
129
Bit
Access
Default
Description
Name
2
IP_TEMP
Reflects if a temperature interrupt is pending
0: No temperature interrupt is pending. The
temperature senors did not detect a temperature that
exceeds the actual limit.
0: No temperature interrupt is pending. The
temperature senors did not detect a temperature that
exceeds the actual limit.
a
1: The temperature interrupt is pending. The
temperature sensor has detected a temperature above
the actual limit.
temperature sensor has detected a temperature above
the actual limit.
0
2
r
3
Reserved
Reserved
0
2
r
4
IP_TIMER1
Reflects if a timer 1 interrupt is pending
0: No timer 1 interrupt is pending.
1: The timer 1 interrupt is pending.
0: No timer 1 interrupt is pending.
1: The timer 1 interrupt is pending.
0
2
r
5
IP_TIMER2
Reflects if a timer 2 interrupt is pending
0: No timer 2 interrupt is pending.
1: The timer 2 interrupt is pending.
0: No timer 2 interrupt is pending.
1: The timer 2 interrupt is pending.
0
2
r
6
IP_ACFAIL
Reflects if a interrupt from the VMEbus ACFAIL signal
is pending
0: No ACFAIL interrupt is pending.
1: The ACFAIL interrupt is pending.
The interrupt can be cleared by writing a 1 to this bit.
is pending
0: No ACFAIL interrupt is pending.
1: The ACFAIL interrupt is pending.
The interrupt can be cleared by writing a 1 to this bit.
0
2
r/w
7
IP_SYSFAIL
Reflects if a interrupt from the VMEbus SYSFAIL signal
is pending
0: No SYSFAIL interrupt is pending.
1: The SYSFAIL interrupt is pending.
The interrupt can be cleared by writing a 1 to this bit.
is pending
0: No SYSFAIL interrupt is pending.
1: The SYSFAIL interrupt is pending.
The interrupt can be cleared by writing a 1 to this bit.
0
2
a
r/w
Reset Register
The reset register is used to identify the last occurred reset. If all bits are cleared (0), the
last reset was a power−on reset. Only one reset status bit can be active at the same time.
Every reset clears the previous reset status bit.
last reset was a power−on reset. Only one reset status bit can be active at the same time.
Every reset clears the previous reset status bit.
Address: 1FF.F160.01D4
16
Table 42:
Reset Status Register
Bit
Name
Description
Default
Access
0
RST KEY
Reflects whether the last reset has been generated by the
front panel reset key
0: Front panel reset key has not been pressed.
1: Front panel reset key has been pressed.
front panel reset key
0: Front panel reset key has not been pressed.
1: Front panel reset key has been pressed.
0
2
r
1
RST SW
Reflects whether the last reset has been generated
through software inside the processor
0: No software reset has occurred.
1: Software reset has occurred.
through software inside the processor
0: No software reset has occurred.
1: Software reset has occurred.
0
2
r