Oracle Vacuum Cleaner CPU-56T User Manual
EBus
Devices’ Features and Data Paths
SPARC/CPU−56T
83
Ethernet Interface 1/3 Switching
As mentioned earlier in this guide, Ethernet interface 1 is available via front panel and
Ethernet interface 3 via the CPU board
Ethernet interface 3 via the CPU board
′s IOBP. Only one of both interfaces can be active at
the same time.
a
The selection which interface is active is made at board reset by the FPGA
′s internal logic.
It depends on the Miscellaneous Control Register bits 5 to 7 and on which Ethernet
interface provides a link. The Miscellaneous Control Register is set by OpenBoot while
booting the board. For information on how to change the default setting, refer to
the
interface provides a link. The Miscellaneous Control Register is set by OpenBoot while
booting the board. For information on how to change the default setting, refer to
the
a
SPARC/CPU−56(T) OpenBoot Enhancements Programmer
4s Guide
a
which is available via
the Force Computers S.M.A.R.T. service.
By default, the selection is made as described in the following table.
a
Link at Interface 1
a
Link at Interface 3
Activated Ethernet Interface
Yes
Yes
1
Yes
No
1
No
Yes
3
No
No
1
LED and Switch Control
The FPGA internal logic is responsible for:
S Control of front panel LEDs
S Readback of switches SW1−4
Reset Control
The FPGA handles all resets and distributes them to the CPU. Possible reset sources are
listed in the following table.
listed in the following table.
a
Table 12:
Reset Sources
Reset Source
Description
Watchdog reset
On expiry, the watchdog timer can generate a
reset.
reset.
a
Front panel key
Depending on the time the key is pressed, either a
reset or a board abort is issued
reset or a board abort is issued
Two−pin connector on CPU board
′s IOBP
By shortcutting this connector a reset is issued
VMEbus
Two directions are possible: the VMEbus resets the
CPU board or the CPU board resets the VME bus
CPU board or the CPU board resets the VME bus