Oracle Vacuum Cleaner CPU-56T User Manual

Reset Source

Description

Power−up reset

If one or more on−board voltages are not within
their thresholds, a reset is issued

PMC reset

A PMC module in non−monarch mode can reset
the CPU board

The following memory devices are connected to the EBus:

S One PLCC PROM with 1 MByte address space

a

S One flash memory device with 16 MByte address space
The PLCC PROM is the device from which the CPU board boots by default.

a

The 16 MByte flash memory device can be used as:

S User flash memory of 16 MBytes
S Boot flash memory of 1 MByte with the remaining 15 MBytes used as user flash

memory

The selection between both operation modes is made via on−board switches.

a

Whether to boot from the PLCC PROM or the flash memory device, is determined by
switch SW1−2. After booting, the whole PLCC PROM is switched off, regardless of the
position of switch SW 1−2. Switch SW1−1 is used to enable write−protection of the flash
memory device. If this switch is OFF (default), the flash memory device is
write−protected. In order to copy the PLCC PROM content to the flash memory device,
switch SW1−1 must be switched ON and switch SW1−2 must be set to OFF.

The CPU board provides the M48T35AV with an real−time clock (RTC) and a non−volatile
RAM (NVRAM) which offers the following features:

S 32 KByte ultra−low power CMOS SRAM
S Byte−wide accessible real−time clock

a

S Long−life lithium carbon mono fluoride battery
S Year−2000 compliant RTC with own crystal

The CPU board provides four independent full−duplex serial I/O interfaces. They are
implemented via the Quad Enhanced Serial Communication Controller 16C554 by Texas
Instruments.