Oracle Vacuum Cleaner CPU-56T User Manual
Devices’ Features and Data Paths
EBus
82
SPARC/CPU−56T
interrupt is generated is set to 1.25s. Once the watchdog timer is running, it is only
possible to reduce the watchdog run out time.
possible to reduce the watchdog run out time.
a
Timer
The FPGA contains two timers which can be used as two independent 16−bit count−down
timers with a timer interval of 10
timers with a timer interval of 10
µs and a maximum run−out time of 655.35 ms. Two
independent interrupts are possible which can be enabled or disabled with the Interrupt
Enable Control register. One counter read−back register set is also available which shows
the correct timer values.
Enable Control register. One counter read−back register set is also available which shows
the correct timer values.
a
Both timers can be combined to run as one 32−bit count−down timer with a timer interval
of 10
of 10
µs and a total run−out time of 42949.67295 s (or 11 h, 55 min, 49 s and 672.95 ms). In
this mode only one interrupt is possible.
a
The timer counts down from its initial value to zero in steps of 10
µs. The initial value can
be set by software from 1 to 65535 in 16−bit mode or from 1 to 4294967295 in the 32−bit
mode, which results in a timer period of 10
mode, which results in a timer period of 10
µs to 655.35 ms in the 16−bit mode or of 10 µs
to 42949.67295s in the 32−bit mode. If the timer has reached zero, an interrupt is
generated, if enabled, and the timer loads its initial value to count down again.
generated, if enabled, and the timer loads its initial value to count down again.
A detailed description of all registers related to the timers is given in the chapter "Maps
and Registers".
and Registers".
a
Temperature Sensor Control
The on−board temperature sensor device MAX1617 measures the temperatures of the
CPU board and the CPU. If the measured temperatures is not within a pre−defined range
between lower and upper temperature, bit 2 is set in the External Failure Register and, if
enabled, an interrupt is generated.
CPU board and the CPU. If the measured temperatures is not within a pre−defined range
between lower and upper temperature, bit 2 is set in the External Failure Register and, if
enabled, an interrupt is generated.
a
Local I2C Interface
Two separate I
2
C buses are available on the CPU board. Both are implemented in the
Xilinx FPGA and have the following devices attached to them:
a
S Serial Presence Detects (SPDs)
S On−board temperature sensor
S Board Information Blocks (BIBs)
BIBs are used for internal purposes only and are therefore not further described in this
guide. All other devices are I2C bus slaves and are identified by unique addresses which
are given in the table below.
S On−board temperature sensor
S Board Information Blocks (BIBs)
BIBs are used for internal purposes only and are therefore not further described in this
guide. All other devices are I2C bus slaves and are identified by unique addresses which
are given in the table below.
Device
I2C Bus
I2C Bus Slave Address
Temperature sensor MAX1617
2
0011.000
2
SPD CPU−56 PROM Bank 1−4 24C04 Serial E
2
PROM
2
1010.00x
2
SPD MEM−550 PROM Bank 1−4 24C04 Serial E
2
PROM
2
1010.01x
2