Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

Product codes
BX80605X3430
Page of 296
Processor Uncore Configuration Registers
200
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.4.4
CCR—Class Code Register
This register contains the Class Code for the device. Writes to this register have 
no effect.
4.4.5
HDR—Header Type Register
This register identifies the header layout of the configuration space.
Device:
0
Function: 0, 1
Offset:
0Eh
Device:
2
Function: 0, 1
Offset:
0Eh
Device:
3
Function: 0, 1, 4
Offset:
0Eh
Device:
4, 5
Function: 0–3
Offset:
0Eh
Bit
Attr
Default
Description
23:16
RO
06h
Base Class
This field indicates the general device category. For the processor, this field 
is hardwired to 06h, indicating it is a “Bridge Device”.
15:8
RO
0
Sub-Class
This field qualifies the Base Class, providing a more detailed specification of 
the device function.
For all devices the default is 00h, indicating “Host Bridge”.
7:0
RO
0
Register-Level Programming Interface
This field identifies a specific programming interface (if any), that device 
independent software can use to interact with the device. There are no 
such interfaces defined for “Host Bridge” types, and this field is hardwired 
to 00h.
Device:
0
Function: 0, 1
Offset:
08h
Device:
2
Function: 0, 1
Offset:
08h
Device:
3
Function: 0, 1, 4
Offset:
08h
Device:
4, 5
Function: 0–3
Offset:
08h
Bit
Attr
Default
Description
7
RO
1
Multi-Function Device
Selects whether this is a multi-function device, that may have alternative 
configuration layouts. This bit is hardwired to 1 for devices in the processor.