Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Processor Uncore Configuration Registers
202
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.4.8
PCICMD—Command Register
This register defines the PCI 3.0 compatible command register values applicable to PCI
Express space.
Express space.
Device:
0
Function: 0, 1
Offset:
2Eh
Device:
2
Function: 0, 1
Offset:
2Eh
Device:
3
Function: 0, 1, 4
Offset:
2Eh
Device:
4, 5
Function: 0–3
Offset:
2Eh
Bit
Attr
Default
Description
15:0
RWO
8086h
Subsystem Identification Number
The default value specifies Intel.
The default value specifies Intel.
Device:
0
Function: 0, 1
Offset:
04h
Device:
2
Function: 0, 1
Offset:
04h
Device:
3
Function: 0, 1, 4
Offset:
04h
Device:
4, 5
Function: 0–3
Offset:
04h
Bit
Attr Default
Description
15:11
RV
0
Reserved. (by PCI-SIG)
10
RO
0
INTxDisable: Interrupt Disable
Controls the ability of the PCI Express port to generate INTx messages.
If this device does not generate interrupts then this bit is not implemented and is RO.
If this device generates interrupts then this bit is RW and this bit disables the
Controls the ability of the PCI Express port to generate INTx messages.
If this device does not generate interrupts then this bit is not implemented and is RO.
If this device generates interrupts then this bit is RW and this bit disables the
device/function from asserting INTx#. A value of 0 enables the assertion of its INTx#
signal. A value of 1 disables the assertion of its INTx# signal.
Legacy Interrupt mode is enabled
Legacy Interrupt mode is enabled
1 = Legacy Interrupt mode is disabled
9
RO
0
FB2B: Fast Back-to-Back Enable
This bit controls whether or not the master can do fast back-to-back writes. Since
This bit controls whether or not the master can do fast back-to-back writes. Since
this device is strictly a target this bit is not implemented. This bit is hardwired to 0.
Writes to this bit position have no effect.
8
RO
0
SERRE: SERR Message Enable
This bit is a global enable bit for this devices SERR messaging. This host bridge will
This bit is a global enable bit for this devices SERR messaging. This host bridge will
not implement SERR messaging. This bit is hardwired to 0. Writes to this bit position
have no effect.If SERR is used for error generation, then this bit must be RW and
enable/disable SERR signaling.