Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
209
Processor Uncore Configuration Registers
4.5.5
SAD_PCIEXBAR
Global register for PCI ExpressXBAR address space.
4.5.6
SAD_TPCIEXBAR
Global register for trusted PCIEXBAR address space. Bus number comes from
PCIEXBAR.
PCIEXBAR.
Device:
0
Function: 1
Offset:
50h
Access as a QWord
Bit
Attr
Default
Description
63:40
RV
0
Reserved
39:20
RW
0
ADDRESS
Base address of PCI ExpressXBAR. Must be naturally aligned to size; low
Base address of PCI ExpressXBAR. Must be naturally aligned to size; low
order bits are ignored.
19:4
RO
0
Reserved
3:1
RW
0
SIZE
Size of the PCI ExpressXBAR address space. (MAX bus number).
000 = 256 MB
001 = Reserved
010 = Reserved
011 = Reserved
100 = Reserved
101 = Reserved
110 = 64 MB
111 = 128 MB
Size of the PCI ExpressXBAR address space. (MAX bus number).
000 = 256 MB
001 = Reserved
010 = Reserved
011 = Reserved
100 = Reserved
101 = Reserved
110 = 64 MB
111 = 128 MB
0
RW
0
ENABLE
Enable for PCI ExpressXBAR address space. Editing size should not be done
Enable for PCI ExpressXBAR address space. Editing size should not be done
without also enabling range.
Device:
0
Function: 1
Offset:
58h
Access as a QWord
Bit
Type
Default
Description
63:40
RV
0
Reserved
39:20
RW
0
ADDRESS
Base address of PCIEXBAR.Must be naturally aligned to size; low order bits are
Base address of PCIEXBAR.Must be naturally aligned to size; low order bits are
ignored.
19:1
RO
0
Reserved
0
RW
0
ENABLE
Enable for PCIEXBAR address space.
Enable for PCIEXBAR address space.