Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Processor Uncore Configuration Registers
210
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.5.7
SAD_MCSEG_BASE
Global register for McSEG address space. These are designed to look just like the cores
SMRR type registers.
SMRR type registers.
4.5.8
SAD_MCSEG_MASK
Global register for McSEG address space. These are designed to look just like the cores
SMRR type registers.
SMRR type registers.
4.5.9
SAD_MESEG_BASE
Register for Intel Management Engine (Intel ME) range base address.
Device:
0
Function: 1
Offset:
60h
Access as a QWord
Bit
Type
Default
Description
63:40
RV
0
Reserved
39:19
RW
0
BASE_ADDRESS
Base address of McSEG. Must be 4K aligned (space must be power of 2
Base address of McSEG. Must be 4K aligned (space must be power of 2
aligned).
18:0
RO
0
Reserved
Device:
0
Function: 1
Offset:
68h
Access as a QWord
Bit
Type
Default
Description
63:40
RV
0
Reserved
39:19
RW
0
MASK
Mask of McSEG. Space must be power of 2 aligned.
Mask of McSEG. Space must be power of 2 aligned.
18:12
RO
0
Reserved
11
RW
0
ENABLE
Is McSeg Enabled.
Is McSeg Enabled.
10
RW
0
LOCK
Is McSeg/Mask register locked.
Is McSeg/Mask register locked.
9:0
RO
0
Reserved
Device:
0
Function: 1
Offset:
70h
Access as a QWord
Bit
Attr
Default
Description
63:40
RV
0
Reserved
39:19
RW
0
BASE ADDRESS
Base address of Intel ME SEG. Must be 4-K aligned (space must be power of
Base address of Intel ME SEG. Must be 4-K aligned (space must be power of
2 aligned).
18:0
RO
0
Reserved