Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
21
Configuration Process and Registers
2.2
Configuration Mechanisms
The processor is the originator of configuration cycles. Internal to the processor
transactions received through both of the below configuration mechanisms are
translated to the same format.
transactions received through both of the below configuration mechanisms are
translated to the same format.
2.2.1
Standard PCI Express* Configuration Mechanism
The following is the mechanism for translating processor I/O bus cycles to configuration
cycles.
cycles.
The PCI specification defines a slot based "configuration space" that allows each device
to contain up to eight functions, with each function containing up to 256, 8-bit
configuration registers. The PCI specification defines two bus cycles to access the PCI
configuration space: Configuration Read and Configuration Write. Memory and I/O
spaces are supported directly by the processor. Configuration space is supported by a
mapping mechanism implemented within the processor.
to contain up to eight functions, with each function containing up to 256, 8-bit
configuration registers. The PCI specification defines two bus cycles to access the PCI
configuration space: Configuration Read and Configuration Write. Memory and I/O
spaces are supported directly by the processor. Configuration space is supported by a
mapping mechanism implemented within the processor.
The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at
I/O address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh
though 0CFFh). To reference a configuration register, a DW I/O write cycle is used to
place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus,
the function within the device and a specific configuration register of the device
function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a configuration
cycle. CONFIG_DATA then becomes a window into the four bytes of configuration space
specified by the contents of CONFIG_ADDRESS. Any read or write to CONFIG_DATA will
result in the processor translating the CONFIG_ADDRESS into the appropriate
configuration cycle.
I/O address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh
though 0CFFh). To reference a configuration register, a DW I/O write cycle is used to
place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus,
the function within the device and a specific configuration register of the device
function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a configuration
cycle. CONFIG_DATA then becomes a window into the four bytes of configuration space
specified by the contents of CONFIG_ADDRESS. Any read or write to CONFIG_DATA will
result in the processor translating the CONFIG_ADDRESS into the appropriate
configuration cycle.
The processor is responsible for translating and routing the processor’s I/O accesses to
the CONFIG_ADDRESS and CONFIG_DATA registers to internal processor configuration
registers, DMI or PCI Express.
the CONFIG_ADDRESS and CONFIG_DATA registers to internal processor configuration
registers, DMI or PCI Express.
2.2.2
PCI Express* Configuration Mechanism
PCI Express extends the configuration space to 4096 bytes per device/function as
compared to 256 bytes allowed by PCI Specification Revision 2.3. PCI Express
configuration space is divided into a PCI 2.3 compatible region, which consists of the
first 256 bytes of a logical device’s configuration space and a PCI Express extended
region which consists of the remaining configuration space.
compared to 256 bytes allowed by PCI Specification Revision 2.3. PCI Express
configuration space is divided into a PCI 2.3 compatible region, which consists of the
first 256 bytes of a logical device’s configuration space and a PCI Express extended
region which consists of the remaining configuration space.
The PCI-compatible region can be accessed using either the Standard PCI Configuration
Mechanism or using the PCI Express Enhanced Configuration Mechanism described in
this section. The extended configuration registers may only be accessed using the PCI
Express Enhanced Configuration Mechanism. To maintain compatibility with PCI
configuration addressing mechanisms, system software must access the extended
configuration space using 32-bit operations (32-bit aligned) only. These 32-bit
operations include byte enables allowing only appropriate bytes within the DWord to be
accessed. Locked transactions to the PCI Express memory mapped configuration
address space are not supported. All changes made using either access mechanism are
equivalent.
Mechanism or using the PCI Express Enhanced Configuration Mechanism described in
this section. The extended configuration registers may only be accessed using the PCI
Express Enhanced Configuration Mechanism. To maintain compatibility with PCI
configuration addressing mechanisms, system software must access the extended
configuration space using 32-bit operations (32-bit aligned) only. These 32-bit
operations include byte enables allowing only appropriate bytes within the DWord to be
accessed. Locked transactions to the PCI Express memory mapped configuration
address space are not supported. All changes made using either access mechanism are
equivalent.
The PCI Express Enhanced Configuration Mechanism utilizes a flat memory-mapped
address space to access device configuration registers. This address space is reported
by the system firmware to the operating system. The register, SAD_PCIEXBAR defines
address space to access device configuration registers. This address space is reported
by the system firmware to the operating system. The register, SAD_PCIEXBAR defines