Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

Product codes
BX80605X3430
Page of 296
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
23
Configuration Process and Registers
2.3
Routing Configuration Accesses
The processor supports two PCI related interfaces: DMI and PCI Express. The processor 
is responsible for routing PCI and PCI Express configuration cycles to the appropriate 
device that is an integrated part of the processor or to one of these two interfaces. 
Configuration cycles to the PCH internal devices and Primary PCI (including 
downstream devices) are routed to the PCH using DMI. Configuration cycles to both the 
PCI Express Graphics PCI compatibility configuration space and the PCI Express 
Graphics extended configuration space are routed to the PCI Express Graphics port 
device or associated link. 
Figure 2-2. Processor Configuration Cycle Flowchart
DW I/O Write to
CONFIG_ADDRESS
with bit 31 = 1
I/O Read/Write to
CONFIG_DATA
Processor Generates
Type 1 Access
to PCI Express
MCH allows cycle to
go to DMI resulting
in Master Abort
Bus# > SEC BUS
Bus#
   SUB BUS
in Bus 0
Dev 1
Bus#  = 0
Device# = 0 &
Function# =  0
Processor Generates
DMI Type 1
Configuration Cycle
Bus# =
SECONDARY BUS
in Bus  0 
Dev 1
Processor 
Claims
Processor 
Claims
Yes
No
Yes
Yes
No
No
Yes
Yes
No
No
Device# = 0
Processor Generates
Type 0 Access
to PCI Express
Yes
MCH Generates
DMI Type 0
Configuration Cycle
No
Device # =  1  &
Dev # 1 Enabled
& Function# = 0
Processor 
Claims
Yes
No
Processor 
Claims
Yes
No
Device # =  2  &
Dev # 2 Enabled
& Function# = 0
Device # =  4  &
Dev # 4 Enabled
& Function# = 0
Dev # 1 
Enabled &
Dev #  1 
Enabled &
Device# = 0 & 
Function# = 0
Processor
Claims
Yes
Device# = 1 & 
Dev#1 Enabled & 
Function# = 0
Processor
Claims
Yes
Device# =2 & 
Dev#2 Enabled & 
Function# = 0
Processor
Claims
Yes
Device# = n & 
Dev#n Enabled & 
Function# = 0
Processor
Claims
Yes
MCH Generates
DMI Type 0
Configuration 
Cycle
No
No
No
No