Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

Intel

Product codes

BX80605X3430

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

223

Processor Uncore Configuration Registers

4.8.2

TAD_INTERLEAVE_LIST_0; TAD_INTERLEAVE_LIST_1

TAD_INTERLEAVE_LIST_2; TAD_INTERLEAVE_LIST_3

TAD_INTERLEAVE_LIST_4; TAD_INTERLEAVE_LIST_5

TAD_INTERLEAVE_LIST_6; TAD_INTERLEAVE_LIST_7

TAD DRAM package assignments. When the corresponding DRAM_RULE hits, a 3-bit
number (determined by mode) is used to index into the Interleave_List Branches to
determine which channel the DRAM request belongs to.

Device:

3

Function: 1

Offset:

C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh

Access as a DWord

Bit

Attr

Default

Description

31:30

RO

0

Reserved

29:28

RW

-

Branch7. Branch (or index) 111 of the Interleave List.
Bits determined from the matching TAD_DRAM_RULE mode.

27:26

RO

-

Reserved

25:24

RW

-

Branch6. Branch (or index) 110 of the Interleave List.
Bits determined from the matching TAD_DRAM_RULE mode.

23:22

RO

-

Reserved

21:20

RW

-

Branch5. Branch (or index) 101 of the Interleave List.
Bits determined from the matching TAD_DRAM_RULE mode.

19:18

RO

-

Reserved

17:16

RW

-

Branch4. Branch (or index) 100 of the Interleave List.
Bits determined from the matching TAD_DRAM_RULE mode.

15:14

RO

-

Reserved

13:12

RW

-

Branch3. Branch (or index) 011 of the Interleave List.
Bits determined from the matching TAD_DRAM_RULE mode.

11:10

RO

-

Reserved

9:8

RW

-

Branch2. Branch (or index) 010 of the Interleave List.
Bits determined from the matching TAD_DRAM_RULE mode.

7:6

RO

-

Reserved

5:4

RW

-

Branch1. Branch (or index) 001 of the Interleave List.
Bits determined from the matching TAD_DRAM_RULE mode.

3:2

RO

-

Reserved

1:0

RW

-

Branch0. Branch (or index) 000 of the Interleave List.
Bits determined from the matching TAD_DRAM_RULE mode.