Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Processor Uncore Configuration Registers
224
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.9
Integrated Memory Controller Test Registers
4.9.1
MC_COR_ECC_CNT_0
MC_COR_ECC_CNT_1
MC_COR_ECC_CNT_2
MC_COR_ECC_CNT_3
Per DIMM counters of correctable ECC errors. The register organization is as follows.
For example, if there are three DIMMs on the channel, MC_COR_ECC_CNT_0 contains
the error counter information for DIMM 0 and DIMM1 on Channel 0.
MC_COR_ECC_CNT_1 contains the error counter information for DIMM2 on Channel 0.
For example, if there are three DIMMs on the channel, MC_COR_ECC_CNT_0 contains
the error counter information for DIMM 0 and DIMM1 on Channel 0.
MC_COR_ECC_CNT_1 contains the error counter information for DIMM2 on Channel 0.
The lower 16-bit of MC_COR_ECC_CNT_0 contains the errors for DIMM0 and the upper
16-bit field contains the errors for DIMM1. The lower 16-bit of MC_COR_ECC_CNT_1
contains the errors for DIMM2. The upper 16 bits of MC_COR_ECC_CNT_1 are not
used. The same organization applies to Channel 1.
16-bit field contains the errors for DIMM1. The lower 16-bit of MC_COR_ECC_CNT_1
contains the errors for DIMM2. The upper 16 bits of MC_COR_ECC_CNT_1 are not
used. The same organization applies to Channel 1.
MC_COR_ECC_CNT_0: Channel 0 DIMM 0/1
MC_COR_ECC_CNT_1: Channel 0 DIMM 2/Rsvd
MC_COR_ECC_CNT_2: Channel 1 DIMM 0/1
MC_COR_ECC_CNT_3: Channel 1 DIMM 2/Rsvd
MC_COR_ECC_CNT_1: Channel 0 DIMM 2/Rsvd
MC_COR_ECC_CNT_2: Channel 1 DIMM 0/1
MC_COR_ECC_CNT_3: Channel 1 DIMM 2/Rsvd
If there are one or two DIMMs on the channel, the lower 16-bit field of
MC_COR_ECC_CNT_0 contains the errors for DIMM0 on Ranks 0 and 1 on Channel 0.
The upper 16-bit field contains information for DIMM0 on Ranks 2 and 3 for a quad rank
DIMM. The same organization follows for DIMM1 for MC_COR_ECC_CNT_1.
MC_COR_ECC_CNT_0 contains the errors for DIMM0 on Ranks 0 and 1 on Channel 0.
The upper 16-bit field contains information for DIMM0 on Ranks 2 and 3 for a quad rank
DIMM. The same organization follows for DIMM1 for MC_COR_ECC_CNT_1.
MC_COR_ECC_CNT_0: Channel 0 DIMM 0 Ranks 0,1/2,3
MC_COR_ECC_CNT_1: Channel 0 DIMM 1 Ranks 0,1/2,3
MC_COR_ECC_CNT_2: Channel 1 DIMM 0 Ranks 0,1/2,3
MC_COR_ECC_CNT_3: Channel 1 DIMM 1 Ranks 0,1/2,3
MC_COR_ECC_CNT_1: Channel 0 DIMM 1 Ranks 0,1/2,3
MC_COR_ECC_CNT_2: Channel 1 DIMM 0 Ranks 0,1/2,3
MC_COR_ECC_CNT_3: Channel 1 DIMM 1 Ranks 0,1/2,3
4.9.2
Integrated Memory Controller Padscan
Device:
3
Function: 2
Offset:
80h, 84h, 88h, 8Ch
Access as a DWord
Bit
Type
Default
Description
31
RW
0
DIMM1_ERR_OVERFLOW. Correctable error overflow on DIMM 1/Rsvd.
30:16
RW
0
DIMM1_COR_ERR. Correctable error count from DIMM 1/Rsvd.
15
RW
0
DIMM0_ERR_OVERFLOW. Correctable error overflow on DIMM 0.
14:0
RW
0
DIMM0_COR_ERR. Correctable error count from DIMM 0.
Table 4-18. Padscan Accessible Parameters (Sheet 1 of 2)
Parameters Accessible
Per channel
Per Rank
Per Strobe (4 pin) Group
Receive Enable Training
Yes
Yes
Yes
RD DQ-DQS Training
Yes
Yes
Yes
WR DQ-DQS Training
Yes
Yes
Yes