Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Processor Uncore Configuration Registers
230
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.9.8
MC_TEST_PAT_GCTR
Pattern Generator Control.
Device:
3
Function: 4
Offset:
A8h
Access as a DWord
Bit
Attr
Default
Description
31:29
RO
0
Reserved
28:24
RW
6
EXP_LOOP_CNT
Sets the length of the test, defined as 2^(EXP_LOOP_CNT).
Sets the length of the test, defined as 2^(EXP_LOOP_CNT).
23:22
RO
0
Reserved
21
RW
0
ERROR_COUNT_STALL
Masks all detected errors until cleared.
Masks all detected errors until cleared.
20
RW1S
0
STOP_TEST
Force exit from Loopback.Pattern.
Force exit from Loopback.Pattern.
19
RW
0
DRIVE_DC_ZERO
Drive 0 on lanes with PAT_DCD asserted.
Drive 0 on lanes with PAT_DCD asserted.
18:14
RO
0
Reserved
13:12
RW
0
PATBUF_WD_SEL
Select word within pattern buffer to be written.
Select word within pattern buffer to be written.
11
RO
0
Reserved
10:9
RW
0
PATBUF_SEL
Select which pattern buffer will be written when MC_TEST_PAT_BA is written.
Select which pattern buffer will be written when MC_TEST_PAT_BA is written.
8:6
RO
0
Reserved
5
RW
0
IGN_REM_PARAM
Slave will ignore remote parameters transmitted in Loopback.Marker.
Slave will ignore remote parameters transmitted in Loopback.Marker.
4
RW
0
ENABLE_LFSR2
Use scrambled output of Pattern Buffer 2.
Use scrambled output of Pattern Buffer 2.
3
RW
0
ENABLE_LFSR1
Use scrambled output of Pattern Buffer 1.
Use scrambled output of Pattern Buffer 1.
2
RW
1
ENABLE_AUTOINV
Inversion pattern register will rotate automatically once per loop.
Inversion pattern register will rotate automatically once per loop.
1
RW
0
STOP_ON_ERROR
Exit Loopback.Pattern upon first detected error.
Exit Loopback.Pattern upon first detected error.
0
RW1S
0
START_TEST
Initiate transition to Loopback.Pattern.
Initiate transition to Loopback.Pattern.