Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
231
Processor Uncore Configuration Registers
4.9.9
MC_TEST_PAT_BA
Memory Test Pattern Generator Buffer.
4.9.10
MC_TEST_PAT_IS
Memory test pattern inversion selection register.
4.9.11
MC_TEST_PAT_DCD
Memory test DC drive register.
Device:
3
Function: 4
Offset:
B0h
Access as a DWord
Bit
Attr
Default
Description
31:0
RW
0
DATA
32-bit window into the indirectly-addressed pattern buffer register space.
32-bit window into the indirectly-addressed pattern buffer register space.
Device:
3
Function: 4
Offset:
BCh
Access as a DWord
Bit
Attr
Default
Description
31:8
RO
0
Reserved
7:0
RW
1
LANE_INVERT
Per-lane selection of normal or inverted pattern
Per-lane selection of normal or inverted pattern
Device:
3
Function: 4
Offset:
C0h
Access as a DWord
Bit
Attr
Default
Description
31:8
RO
0
Reserved
7:0
RW
0
LANE_DRIVE_DC
Per-lane selection of DC pattern
Per-lane selection of DC pattern