Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Processor Uncore Configuration Registers
244
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.10.14 MC_CHANNEL_0_CKE_TIMING
MC_CHANNEL_1_CKE_TIMING
This register contains parameters that specify the CKE timings. All units are in DCLK.
Device:
4, 5
Function: 0
Offset:
90h
Access as a DWord
Bit
Attr
Default
Description
31:24
RW
0
tRANKIDLE
Rank will go into powerdown after it has been idle for the specified number
Rank will go into powerdown after it has been idle for the specified number
of DCLKs. tRANKIDLE covers max(txxxPDEN). Minimum value is
tWRAPDEN. If CKE is being shared between ranks then both ranks must be
idle for this amount of time. A Power Down Entry command will be
requested for a rank after this number of DCLKs if no request to the rank is
in the MC.
23:21
RW
0
tXP
Minimum delay from exit power down with DLL and any valid command.
Minimum delay from exit power down with DLL and any valid command.
Exit Precharge Power Down with DLL frozen to commands not requiring a
locked DLL. Slow exit precharge powerdown is not supported.
20:11
RW
0
tXSDLL
Minimum delay between the exit of self refresh and commands that
Minimum delay between the exit of self refresh and commands that
require a locked DLL.
10:3
RW
0
tXS
Minimum delay between the exit of self refresh and commands not
Minimum delay between the exit of self refresh and commands not
requiring a DLL.
2:0
RW
0
tCKE
CKE minimum pulse width.
CKE minimum pulse width.