Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

245

This register contains parameters that specify ZQ timing. All units are DCLK unless 
otherwise specified. The register encodings are specified where applicable.

This register contains parameters that specify Rcomp timings.

31

RO

0

30

RW

1

Parallel_ZQ
Enable ZQ calibration to different ranks in parallel.

29

RW

1

tZQenable
Enable the issuing of periodic ZQCS calibration commands.

28:8

RW

16410

ZQ_Interval
Nominal interval between periodic ZQ calibration in increments of tREFI.

7:5

RW

4

tZQCS
Specifies ZQCS cycles in increments of 16. This is the minimum delay 

between ZQCS and any other command. This register should be 

programmed to at least 64/16=4='100' to conform to the DDR3 

specification.

4:0

RW

0

tZQInit
Specifies ZQInit cycles in increments of 32. This is the minimum delay 

between ZQCL and any other command. This register should be 

programmed to at least 512/32=16='10000' to conform to the DDR3 

specification. 

31:17

RO

0

16

RW

0

RCOMP_EN
Enable Rcomp. When set, the Integrated Memory Controller will do the 

programmed blocking of requests and send indications.

15:10

RW

2

RCOMP_CMD_DCLK
Delay from the start of an RCOMP command blocking period in which the 

command rcomp update is done. Program this field to 15 for all 

configurations.

9:4

RW

9

RCOMP_LENGTH
Number of Dclks during which all commands are blocked for an RCOMP 

update. Data RCOMP update is done on the last DCLK of this period. Program 

this field to 31 for all configurations.

3:0

RW

0

RCOMP_INTERVAL
Duration of interval between Rcomp in increments of tRefI. Register value is 

tRefI–1. For example a setting of 0 will produce an interval of tRefI.