Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
261
Processor Uncore Configuration Registers
4.11.4
MC_SAG_CH1_0; MC_SAG_CH1_1; MC_SAG_CH1_2;
MC_SAG_CH1_3; MC_SAG_CH1_4; MC_SAG_CH1_5;
MC_SAG_CH1_6; MC_SAG_CH1_7
Channel Segment Address Registers. For each of the 8 interleave ranges, they specify
the offset between the System Address and the Memory Address and the System
Address bits used for level 1 interleave, which should not be translated to Memory
Address bits. The first stage of Memory Address calculation using System Address and
the contents of these registers is done by the following algorithm:
the offset between the System Address and the Memory Address and the System
Address bits used for level 1 interleave, which should not be translated to Memory
Address bits. The first stage of Memory Address calculation using System Address and
the contents of these registers is done by the following algorithm:
m[39:16] = SystemAddress[39:16] – (2’s complement {Offset[23:0]});
m[15:6] = SystemAddress[15:6];
If (Removed[2]) {Bit 8 removed};
If (Removed[1]) {Bit 7 removed};
If (Removed[0]) {Bit 6 removed};
MemoryAddress[36:6] = m[36:6];
Removed Div3 Interleave
m[15:6] = SystemAddress[15:6];
If (Removed[2]) {Bit 8 removed};
If (Removed[1]) {Bit 7 removed};
If (Removed[0]) {Bit 6 removed};
MemoryAddress[36:6] = m[36:6];
Removed Div3 Interleave
000 0 None
001 0 2-way
011 0 4-way
000 1 3-way
001 1 6-way
001 0 2-way
011 0 4-way
000 1 3-way
001 1 6-way
All other combinations are not supported.
Device:
5
Function: 1
Offset:
80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch
Access as a DWord
Bit
Attr
Default
Description
31:28
RO
0
Reserved
27
RW
0
DIVBY3
This bit tells us that the rule is a 3 or 6 way interleave.
This bit tells us that the rule is a 3 or 6 way interleave.
26:24
RW
0
REMOVED
These are the bits to be removed after offset subtraction. These bits
These are the bits to be removed after offset subtraction. These bits
correspond to System Address [8,7,6].
23:0
RW
0
OFFSET
This value should be subtracted from the current system address to create
This value should be subtracted from the current system address to create
a contiguous address space within a channel. BITS 9:0 ARE RESERVED
AND MUST ALWAYS BE SET TO 0.