Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Processor Uncore Configuration Registers
262
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.12
Integrated Memory Controller Channel Rank
Registers
4.12.1
MC_RIR_LIMIT_CH0_0; MC_RIR_LIMIT_CH0_1;
MC_RIR_LIMIT_CH0_2; MC_RIR_LIMIT_CH0_3;
MC_RIR_LIMIT_CH0_4; MC_RIR_LIMIT_CH0_5;
MC_RIR_LIMIT_CH0_6; MC_RIR_LIMIT_CH0_7
Channel 0 Rank Limit Range Registers.
4.12.2
MC_RIR_LIMIT_CH1_0; MC_RIR_LIMIT_CH1_1;
MC_RIR_LIMIT_CH1_2; MC_RIR_LIMIT_CH1_3;
MC_RIR_LIMIT_CH1_4; MC_RIR_LIMIT_CH1_5;
MC_RIR_LIMIT_CH1_6; MC_RIR_LIMIT_CH1_7
Channel 1 Rank Limit Range Registers.
Device:
4
Function: 2
Offset:
40h, 44h, 48h, 4Ch, 50h, 54h, 58h, 5Ch
Access as a DWord
Bit
Attr
Default
Description
31:10
RO
0
Reserved
9:0
RW
0
LIMIT
This specifies the top of the range being mapped to the ranks specified in
This specifies the top of the range being mapped to the ranks specified in
the MC_RIR_WAY_CH registers. The most significant bits of the lowest
address in this range is one greater than the limit field in the RIR register
with the next lower index. This field is compared against MA[37:28].
Device:
5
Function: 2
Offset:
40h, 44h, 48h, 4Ch, 50h, 54h, 58h, 5Ch
Access as a DWord
Bit
Attr
Default
Description
31:10
RO
0
Reserved
9:0
RW
0
LIMIT
This specifies the top of the range being mapped to the ranks specified in the
This specifies the top of the range being mapped to the ranks specified in the
MC_RIR_WAY_CH registers. The most significant bits of the lowest address in
this range is one greater than the limit field in the RIR register with the next
lower index. This field is compared against MA[37:28].