Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
277
System Address Map
5.2.4.1
Relocatable TSEG
These are system DRAM memory regions that are used for SMM/CMM mode operation.
IIO would completer abort all inbound transactions that target these address ranges.
IIO should not receive transactions that target these addresses in the outbound
direction, but IIO does not explicitly check for this error condition but rather
subtractively forwards such transactions to the subtractive decode port of the IIO, if
one exists downstream else it is master aborted.
IIO would completer abort all inbound transactions that target these address ranges.
IIO should not receive transactions that target these addresses in the outbound
direction, but IIO does not explicitly check for this error condition but rather
subtractively forwards such transactions to the subtractive decode port of the IIO, if
one exists downstream else it is master aborted.
The location (1-MB aligned) and size (from 512 KB to 8 MB) in IIO can be programmed
by software.
by software.
5.2.5
Address Region from TOLM to 4 GB
5.2.5.1
PCI Express Memory Mapped Configuration Space
This is the system address region that is allocated for software to access the PCI
Express Configuration Space. This region is relocatable below 4 GB by BIOS/firmware
and IIO has no explicit knowledge of this address range. It is the responsibility of
software to make sure that this system address range is not included in any of the
system DRAM memory ranges that IIO decodes inbound. If software were to mis-
program IIO in this way, accesses to this space could potentially be sent to the
processor by the IIO.
Express Configuration Space. This region is relocatable below 4 GB by BIOS/firmware
and IIO has no explicit knowledge of this address range. It is the responsibility of
software to make sure that this system address range is not included in any of the
system DRAM memory ranges that IIO decodes inbound. If software were to mis-
program IIO in this way, accesses to this space could potentially be sent to the
processor by the IIO.
Address Region
From
To
TSEG
FE00_0000h (default)
FE7F_FFFFh (default)
Figure 5-3. Pre-allocated Memory Example for 64 MB DRAM, 1 MB VGA, 1 MB GTT Stolen
and 1 MB TSEG
Memory Segments
Attributes
Comments
0000_0000h – 03CF_FFFFh
R/W
Available System Memory 61 MB
03D0_0000h – 03DF_FFFFh
SMM Mode Only -
processor Reads
TSEG Address Range & Pre-allocated Memory
03E0_0000h – 03EF_FFFFh
R/W
Pre-allocated Graphics VGA memory.
1 MB (or 4/8/16/32/64/128/256 MB) when IGD is
1 MB (or 4/8/16/32/64/128/256 MB) when IGD is
enabled.
03F0_0000h – 03FF_FFFFh
R/W
Pre-allocated Graphics GTT stolen memory.
1 MB (or 2 MB) when IGD is enabled.
1 MB (or 2 MB) when IGD is enabled.