Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
275
System Address Map
5.2.3
VGA/SMM and Legacy C/D/E/F Regions
shows the memory address regions below 1 MB. These regions are legacy
access ranges.
5.2.3.1
VGA/SMM Memory Space
This legacy address range is used by video cards to map a frame buffer or a character-
based video buffer. By default, accesses to this region are forwarded to main memory
by the processor. However, once firmware figures out where the VGA device is in the
system, it sets up the processor’s source address decoders to forward these accesses
to the IIO. Within IIO, if the VGAEN bit is set in the PCI bridge control register (BCTRL)
of a PCIe port, then transactions within the VGA space (defined above) are forwarded
to the associated port, regardless of the settings of the peer-to-peer memory address
ranges of that port. If none of the PCIe ports have the VGAEN bit set (note that per the
IIO address map constraints the VGA memory addresses cannot be included as part of
the normal peer-to-peer bridge memory apertures in the root ports), then these
accesses are forwarded to the subtractive decode port. Also refer to the PCI-PCI Bridge
1.2 Specification for further details on the VGA decoding. Note that only one VGA
device may be enabled per system partition. The VGAEN bit in the PCIe bridge control
register must be set only in one PCIe port in a system partition. IIO does not support
the MDA (monochrome display adapter) space independent of the VGA space.
based video buffer. By default, accesses to this region are forwarded to main memory
by the processor. However, once firmware figures out where the VGA device is in the
system, it sets up the processor’s source address decoders to forward these accesses
to the IIO. Within IIO, if the VGAEN bit is set in the PCI bridge control register (BCTRL)
of a PCIe port, then transactions within the VGA space (defined above) are forwarded
to the associated port, regardless of the settings of the peer-to-peer memory address
ranges of that port. If none of the PCIe ports have the VGAEN bit set (note that per the
IIO address map constraints the VGA memory addresses cannot be included as part of
the normal peer-to-peer bridge memory apertures in the root ports), then these
accesses are forwarded to the subtractive decode port. Also refer to the PCI-PCI Bridge
1.2 Specification for further details on the VGA decoding. Note that only one VGA
device may be enabled per system partition. The VGAEN bit in the PCIe bridge control
register must be set only in one PCIe port in a system partition. IIO does not support
the MDA (monochrome display adapter) space independent of the VGA space.
Figure 5-2. VGA/SMM and Legacy C/D/E/F Regions
Address Region
From
To
VGA
000_000A_0000h
000_000B_FFFFh
1MB
640 KB
768 KB
0C0000h
0A0000h
VGA/SMM
Regions
0B8000h
0B0000h
736 KB
704 KB
Controlled by
VGA Enable
and SMM Enable
in CPU
VGA Enable
and SMM Enable
in CPU
Key
= Low BIOS
= VGA/SMM
= System Memory (DOS)
BIOS, Shadow
RAM accesses -
Controlled at 16K
granularity in C PU
Source decoder
RAM accesses -
Controlled at 16K
granularity in C PU
Source decoder