Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

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Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

If any of the following conditions are violated the results of SMM accesses are 
unpredictable and may cause the system to hang: 

1. The Compatible SMM space must not be set-up as cacheable.
2. High or TSEG SMM transaction address space must not overlap address space 

assigned to system DRAM, or to any “PCI” devices (including DMI Interface, and 
PCI Express, and graphics devices). This is a BIOS responsibility.

3. Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
4. When TSEG SMM space is enabled, the TSEG space must not be reported to the 

OS as available DRAM. This is a BIOS responsibility. 

5. Any address translated through the GMADR TLB must not target DRAM from 

A_0000h–F_FFFFh.

When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1) the Compatible SMM 
space is effectively disabled. Processor originated accesses to the Compatible SMM 
space are forwarded to PCI Express if VGAEN=1 (also depends on MDAP), otherwise 
they are forwarded to the DMI Interface. PCI Express and DMI Interface originated 
accesses are never allowed to access SMM space.

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