Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
System Address Map
282
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
5.3.2
ISA Addresses
IIO supports ISA addressing per the PCI-PCI Bridge 1.2 Specification. ISA addressing is
enabled in a PCIe port using the ISAEN bit in the bridge configuration space. Note that
when VGAEN bit is set in a PCIe port without the VGA16DECEN bit being set, the ISAEN
bit must be set in all the peer PCIe ports in the system.
enabled in a PCIe port using the ISAEN bit in the bridge configuration space. Note that
when VGAEN bit is set in a PCIe port without the VGA16DECEN bit being set, the ISAEN
bit must be set in all the peer PCIe ports in the system.
5.3.3
CFC/CF8 Addresses
These addresses are used by legacy operating systems to generate PCI configuration
cycles. These have been replaced with a memory-mapped configuration access
mechanism in PCI Express (which only PCI Express aware operating systems utilize).
That said, IIO does not explicitly decode these I/O addresses and take any specific
action. These accesses are decoded as part of the normal inbound and outbound I/O
transaction flow and follow the same routing rules. Refer also to
cycles. These have been replaced with a memory-mapped configuration access
mechanism in PCI Express (which only PCI Express aware operating systems utilize).
That said, IIO does not explicitly decode these I/O addresses and take any specific
action. These accesses are decoded as part of the normal inbound and outbound I/O
transaction flow and follow the same routing rules. Refer also to
for further details of I/O address decoding in IIO.
5.3.4
PCIe Device I/O Addresses
These addresses could be anywhere in the 64KB I/O space and are used to allocate I/O
addresses to PCIe devices. Each IIO is allocated a chunk of I/O address space and
there are IIO-specific requirements on how these chunks are distributed amongst IIOs
to support peer-to-peer. Refer to
addresses to PCIe devices. Each IIO is allocated a chunk of I/O address space and
there are IIO-specific requirements on how these chunks are distributed amongst IIOs
to support peer-to-peer. Refer to
for details of these restrictions. Each IIO
has a couple of IO address range registers (LIO and GIO) to support local and remote
peer-to-peer in the IO address range (debug mode only). Refer to section
peer-to-peer in the IO address range (debug mode only). Refer to section
for details of how these registers are used in the inbound and
outbound IO address decoding.
5.4
Configuration/CSR Space
There are two types of configuration/CSR space in IIO - PCIe configuration space and
Intel QuickPath Interconnect CPUCSR space. PCIe configuration space is the standard
PCIe configuration space defined in the PCIe specification. CSR space is memory
mapped space used exclusively for special processor registers.
Intel QuickPath Interconnect CPUCSR space. PCIe configuration space is the standard
PCIe configuration space defined in the PCIe specification. CSR space is memory
mapped space used exclusively for special processor registers.
5.4.1
PCIe Configuration Space
PCIe configuration space allows for upto 256 buses, 32 devices per bus and 8 functions
per device. There could be multiple groups of these configuration spaces and each is
called a segment. IIO can support multiple segments in a system. But each IIO can
span one segment and no peer-to-peer accesses are allowed between segments.
Within each IIO there are multiple devices that are in the PCIe configuration space. All
these devices are accessed using NcCfgWr/Rd transactions on Intel QuickPath
Interconnect. Within each segment, bus 0 is always assigned to the internal bus
number of IIO which has the legacy PCH attached to it. Refer to
per device. There could be multiple groups of these configuration spaces and each is
called a segment. IIO can support multiple segments in a system. But each IIO can
span one segment and no peer-to-peer accesses are allowed between segments.
Within each IIO there are multiple devices that are in the PCIe configuration space. All
these devices are accessed using NcCfgWr/Rd transactions on Intel QuickPath
Interconnect. Within each segment, bus 0 is always assigned to the internal bus
number of IIO which has the legacy PCH attached to it. Refer to
for details of IIO configuration transaction decoding.
Each IIO is allocated a chunk of PCIe bus numbers and there are IIO-specific
requirements on how these chunks are distributed amongst IIOs to support peer-to-
peer. Refer to
requirements on how these chunks are distributed amongst IIOs to support peer-to-
peer. Refer to
for details of these restrictions. Each IIO has a couple of
configuration bus range registers (LCFGBUS and GCFGBUS) to support local and