Motorola MPC8260 User Manual
MOTOROLA
Chapter 7. 60x Signals
7-3
Part III. The Hardware Interface
7.2 Signal Descriptions
This section describes individual MPC8260 60x signals, grouped according to Figure 7-1.
Note that the following sections brießy summarize signal functions. Chapter 8, ÒThe 60x
Bus,Ó describes many of these signals in greater detail, both in terms of their function and
how groups of signals interact.
Note that the following sections brießy summarize signal functions. Chapter 8, ÒThe 60x
Bus,Ó describes many of these signals in greater detail, both in terms of their function and
how groups of signals interact.
7.2.1 Address Bus Arbitration Signals
The address arbitration signals are a collection of input and output signals devices use to
request address bus mastership, recognize when the request is granted, and indicate to other
devices when mastership is granted. For a detailed description of how these signals interact,
see Section 8.4.1, ÒAddress Arbitration.Ó
request address bus mastership, recognize when the request is granted, and indicate to other
devices when mastership is granted. For a detailed description of how these signals interact,
see Section 8.4.1, ÒAddress Arbitration.Ó
Bus arbitration signals have no meaning in internal-only mode.
7.2.1.1 Bus Request (BR)ÑOutput
The bus request (BR) signal is both an input and an output signal on the MPC8260.
7.2.1.1.1 Address Bus Request (BR)ÑOutput
Following are the state meaning and timing comments for the BR signal output in external
master mode.
Following are the state meaning and timing comments for the BR signal output in external
master mode.
State Meaning
AssertedÑIndicates that MPC8260 is requesting mastership of the
address bus. Note that BR may be asserted for one or more cycles
and then deasserted due to an internal cancellation of the bus request
(for example, due to a load hit in the touch load buffer). See
Section 8.4.1, ÒAddress Arbitration.Ó
address bus. Note that BR may be asserted for one or more cycles
and then deasserted due to an internal cancellation of the bus request
(for example, due to a load hit in the touch load buffer). See
Section 8.4.1, ÒAddress Arbitration.Ó
NegatedÑIndicates that the MPC8260 is not requesting the address
bus. The MPC8260 may have no bus operation pending, it may be
parked, or the ARTRY input was asserted on the previous bus clock
cycle.
bus. The MPC8260 may have no bus operation pending, it may be
parked, or the ARTRY input was asserted on the previous bus clock
cycle.
Timing Comments
AssertionÑMay occur on any cycle; does not occur if the MPC8260
is parked and the address bus is idle (BG asserted and ABB input
negated).
is parked and the address bus is idle (BG asserted and ABB input
negated).
NegationÑOccurs for at least one cycle following a qualiÞed BG
even if another transaction is pending; also negated for at least one
cycle following any qualiÞed ARTRY on the bus unless MPC8260
asserted ARTRY and requires a snoop copyback; may also be
negated if MPC8260 cancels the bus request internally before
receiving a qualiÞed BG.
even if another transaction is pending; also negated for at least one
cycle following any qualiÞed ARTRY on the bus unless MPC8260
asserted ARTRY and requires a snoop copyback; may also be
negated if MPC8260 cancels the bus request internally before
receiving a qualiÞed BG.
High ImpedanceÑOccurs during a hard reset or checkstop condition