Motorola MPC8260 User Manual
7-4
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part III. The Hardware Interface
7.2.1.1.2 Address Bus Request (BR)ÑInput
Following are the state meaning and timing comments for the BR signal input in external
master mode.
Following are the state meaning and timing comments for the BR signal input in external
master mode.
State Meaning
AssertedÑIndicates that the external master has a bus transaction to
perform and is waiting for a qualiÞed BG to begin the address tenure.
BR may be asserted even if the two possible pipelined address
tenures have already been granted.
perform and is waiting for a qualiÞed BG to begin the address tenure.
BR may be asserted even if the two possible pipelined address
tenures have already been granted.
NegatedÑIndicates that the external master has no bus transaction to
perform, or if the device is parked, that it is potentially ready to start
a bus transaction on the next clock cycle (with proper qualiÞcation,
see BG).
perform, or if the device is parked, that it is potentially ready to start
a bus transaction on the next clock cycle (with proper qualiÞcation,
see BG).
Timing Comments
AssertionÑMay occur on any cycle; does not occur if the external
master is parked and the address bus is idle (BG asserted and ABB
input negated).
master is parked and the address bus is idle (BG asserted and ABB
input negated).
NegationÑOccurs for at least one cycle after a qualiÞed BG even if
another transaction is pending; also negated for at least one cycle
following any qualiÞed ARTRY on the bus unless this chip asserted
the ARTRY and requires to perform a snoop copyback; may also be
negated if the external master cancels a bus request internally before
receiving a qualiÞed BG.
another transaction is pending; also negated for at least one cycle
following any qualiÞed ARTRY on the bus unless this chip asserted
the ARTRY and requires to perform a snoop copyback; may also be
negated if the external master cancels a bus request internally before
receiving a qualiÞed BG.
High ImpedanceÑOccurs during a hard reset or checkstop
condition.
condition.
7.2.1.2 Bus Grant (BG)
The address bus grant (BG) signal is both an input and an output signal.
7.2.1.2.1 Bus Grant (BG)ÑInput
The following are the state meaning and timing comments for the BG signal input in
external master mode.
The following are the state meaning and timing comments for the BG signal input in
external master mode.
State Meaning
AssertedÑIndicates that the MPC8260 may, with the proper
qualiÞcation, begin a bus transaction and assume ownership of the
address bus. A qualiÞed bus grant is generally determined from the
bus state as follows: QBG = BG ¥ ÂABB ¥ ÂARTRY where ARTRY
is asserted only during the cycle after AACK. Note that the assertion
of BR is not required for a qualiÞed bus grant (for bus parking).
qualiÞcation, begin a bus transaction and assume ownership of the
address bus. A qualiÞed bus grant is generally determined from the
bus state as follows: QBG = BG ¥ ÂABB ¥ ÂARTRY where ARTRY
is asserted only during the cycle after AACK. Note that the assertion
of BR is not required for a qualiÞed bus grant (for bus parking).
NegatedÑIndicates that the MPC8260 is not granted next address
ownership.
ownership.
Timing Comments
AssertionÑMay occur on any cycle. Once the MPC8260 has
assumed address bus ownership, it does not begin checking for BG
again until the cycle after AACK.
assumed address bus ownership, it does not begin checking for BG
again until the cycle after AACK.