Motorola MPC8260 User Manual
MOTOROLA
Chapter 7. 60x Signals
7-7
Part III. The Hardware Interface
Timing Comments
Assertion/NegationÑMust be asserted for one cycle only and then
immediately negated. Assertion may occur at any time during the
assertion of ABB.
immediately negated. Assertion may occur at any time during the
assertion of ABB.
7.2.3 Address Transfer Signals
In internal only mode the memory controller uses these signals for glueless address
transfers to memory and I/O devices.
transfers to memory and I/O devices.
The address transfer signals are used to transmit the address.
7.2.3.1 Address Bus (A[0Ð31])
The address bus (A[0Ð31]) consists of 32 signals that are both input and output signals.
7.2.3.1.1 Address Bus (A[0Ð31])ÑOutput
Following are the state meaning and timing comments for the A[0Ð31] output signals.
Following are the state meaning and timing comments for the A[0Ð31] output signals.
State Meaning
ContentÑSpeciÞes the physical address of the bus transaction. For
burst or extended operations, the address is a double-word.
burst or extended operations, the address is a double-word.
Timing Comments
Assertion/NegationÑDriven valid on the same cycle that TS is
driven/asserted; remains driven/valid for the duration of the address
tenure.
driven/asserted; remains driven/valid for the duration of the address
tenure.
High ImpedanceÑ Occurs the cycle following the assertion of
AACK; no precharge action performed on release.
AACK; no precharge action performed on release.
7.2.3.1.2 Address Bus (A[0Ð31])ÑInput
Following are the state meaning and timing comments for the A[0Ð31] input signals.
Following are the state meaning and timing comments for the A[0Ð31] input signals.
State Meaning
AssertedÑIndicates that another device has begun a bus transaction
and that the address bus and transfer attribute signals are valid for
snooping and in slave mode.
and that the address bus and transfer attribute signals are valid for
snooping and in slave mode.
NegatedÑHas no special meaning.
Timing Comments
Assertion/NegationÑMust be valid on the same cycle that TS is
asserted; sampled by the processor only on this cycle.
asserted; sampled by the processor only on this cycle.
7.2.4 Address Transfer Attribute Signals
In internal only mode the address transfer attribute signals have no meaning.
The transfer attribute signals are a set of signals that further characterize the transferÑsuch
as the size of the transfer, whether it is a read or write operation, and whether it is a burst
or single-beat transfer. For a detailed description of how these signals interact, see
Section 7.2.4, ÒAddress Transfer Attribute Signals.Ó
as the size of the transfer, whether it is a read or write operation, and whether it is a burst
or single-beat transfer. For a detailed description of how these signals interact, see
Section 7.2.4, ÒAddress Transfer Attribute Signals.Ó