Motorola MPC8260 User Manual
7-6
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part III. The Hardware Interface
7.2.1.3.2 Address Bus Busy (ABB)ÑInput
Following are the state meaning and timing comments for the ABB input signal.
Following are the state meaning and timing comments for the ABB input signal.
State Meaning
AssertedÑIndicates that external device is the address bus master.
NegatedÑIndicates that the address bus may be available for use by
the MPC8260 (see BG). The MPC8260 also tracks the state of ABB
on the bus from the TS and AACK inputs. (See section on address
arbitration phase.)
the MPC8260 (see BG). The MPC8260 also tracks the state of ABB
on the bus from the TS and AACK inputs. (See section on address
arbitration phase.)
Timing Comments
AssertionÑMay occur whenever the MPC8260 must be prevented
from using the address bus.
from using the address bus.
NegationÑMay occur whenever the MPC8260 may use the address
bus.
bus.
7.2.2 Address Transfer Start Signal
In the internal only mode the address transfer start signal has no meaning.
Address transfer start signal are input and output signals that indicate that an address bus
transfer has begun.
transfer has begun.
7.2.2.1 Transfer Start (TS)
The TS signal is both an input and an output signal on the MPC8260.
7.2.2.1.1 Transfer Start (TS)ÑOutput
Following are the state meaning and timing comments for the TS output signal.
Following are the state meaning and timing comments for the TS output signal.
State Meaning
AssertedÑIndicates that the MPC8260 has started a bus transaction
and that the address bus and transfer attribute signals are valid. It is
also an implied data bus request if the transfer attributes TT[0Ð4]
indicate that a data tenure is required for the transaction.
and that the address bus and transfer attribute signals are valid. It is
also an implied data bus request if the transfer attributes TT[0Ð4]
indicate that a data tenure is required for the transaction.
NegatedÑHas no special meaning during a normal transaction.
Timing Comments
Assertion/NegationÑDriven and asserted on the cycle after a
qualiÞed BG is accepted by MPC8260; remains asserted for one
clock only. Negated for the remainder of the address tenure.
Assertion is coincident with the Þrst clock that ABB is asserted.
qualiÞed BG is accepted by MPC8260; remains asserted for one
clock only. Negated for the remainder of the address tenure.
Assertion is coincident with the Þrst clock that ABB is asserted.
High ImpedanceÑOccurs the cycle following the assertion of
AACK (same cycle as ABB negation).
AACK (same cycle as ABB negation).
7.2.2.2 Transfer Start (TS)ÑInput
Following are the state meaning and timing comments for the TS input signal.
State Meaning
AssertedÑIndicates that another device has begun a bus transaction
and that the address bus and transfer attribute signals are valid for
snooping.
and that the address bus and transfer attribute signals are valid for
snooping.
NegatedÑHas no special meaning.