Motorola MPC8260 User Manual
7-16
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part III. The Hardware Interface
NegatedÑ(During assertion of DBB) indicates that, until TA is
asserted, the MPC8260 must continue to drive the data for the
current write or must wait to sample the data for reads.
asserted, the MPC8260 must continue to drive the data for the
current write or must wait to sample the data for reads.
Timing Comments
AssertionÑMust not occur before AACK for the current transaction
(if the address retry mechanism is to be used to prevent invalid data
from being used by the MPC8260); otherwise, assertion may occur
at any time during the assertion of DBB. The system can withhold
assertion of TA to indicate that the MPC8260 should insert wait
states to extend the duration of the data beat.
NegationÑMust occur after the bus clock cycle of the Þnal (or only)
data beat of the transfer. For a burst transfer, the system can assert TA
for one bus clock cycle and then negate it to advance the burst
transfer to the next beat and insert wait states during the next beat.
(Note: when conÞgured for 1:1 clock mode and is performing a burst
read into the data cache, the MPC8260 requires two wait states
between the assertion of TS and the Þrst assertion of TA for that
transaction, or one wait state for 1.5:1 clock mode.)
(if the address retry mechanism is to be used to prevent invalid data
from being used by the MPC8260); otherwise, assertion may occur
at any time during the assertion of DBB. The system can withhold
assertion of TA to indicate that the MPC8260 should insert wait
states to extend the duration of the data beat.
NegationÑMust occur after the bus clock cycle of the Þnal (or only)
data beat of the transfer. For a burst transfer, the system can assert TA
for one bus clock cycle and then negate it to advance the burst
transfer to the next beat and insert wait states during the next beat.
(Note: when conÞgured for 1:1 clock mode and is performing a burst
read into the data cache, the MPC8260 requires two wait states
between the assertion of TS and the Þrst assertion of TA for that
transaction, or one wait state for 1.5:1 clock mode.)
7.2.8.1.2 Transfer Acknowledge (TA)ÑOutput
Following are the state meaning and timing comments for TA as an output signal.
Following are the state meaning and timing comments for TA as an output signal.
State Meaning
AssertedÑIndicates that the data has been latched for a write
operation, or that the data is valid for a read operation, thus
terminating the current data beat. If it is the last or only data beat, this
also terminates the data tenure.
NegatedÑIndicates that master must extend the current data beat
(insert wait states) until data can be provided or accepted by the
MPC8260.
operation, or that the data is valid for a read operation, thus
terminating the current data beat. If it is the last or only data beat, this
also terminates the data tenure.
NegatedÑIndicates that master must extend the current data beat
(insert wait states) until data can be provided or accepted by the
MPC8260.
Timing Comments
AssertionÑOccurs on the clock in which the current data transfer
can be completed.
can be completed.
NegationÑOccurs after the clock cycle of the Þnal (or only) data
beat of the transfer. For a burst transfer, TA may be negated between
beats to insert one or more wait states before the completion of the
next beat.
beat of the transfer. For a burst transfer, TA may be negated between
beats to insert one or more wait states before the completion of the
next beat.
7.2.8.2 Transfer Error Acknowledge (TEA)
The transfer error acknowledge (TEA) signal is both input and output on the MPC8260,
This signal can be ignored if BCR[TEA_EN] is cleared.
This signal can be ignored if BCR[TEA_EN] is cleared.
7.2.8.2.1 Transfer Error Acknowledge (TEA)ÑInput
Following are the state meaning and timing comments for the TEA input signal.
Following are the state meaning and timing comments for the TEA input signal.
State Meaning
AssertedÑIndicates that a bus error occurred. The assertion of TEA
causes the negation/high impedance of DBB in the next clock cycle.
However, data entering the MPC8260 internal memory resources
such as GPRs or caches are not invalidated.
causes the negation/high impedance of DBB in the next clock cycle.
However, data entering the MPC8260 internal memory resources
such as GPRs or caches are not invalidated.