Motorola MPC8260 User Manual

10-40

MPC8260 PowerQUICC II UserÕs Manual

MOTOROLA

Part III. The Hardware Interface

10.4.6.3 Column Address to First Data OutÑCAS Latency

This parameter, controlled by P/LSDMR[CL], deÞnes the timing for Þrst read data after a
column address is sampled by the SDRAM.

Figure 10-22. CL = 2 (2 Clock Cycles)

10.4.6.4 Last Data Out to Precharge

This parameter, controlled by P/LSDMR[LDOTOPRE], deÞnes the earliest timing for the

PRECHARGE

command after the last data was read from the SDRAM. It is always related to

the CL parameter.

Figure 10-23. LDOTOPRE = 2 (-2 Clock Cycles)

CLK

ALE

CSn

SDRAS

SDCAS

MA[0Ð11]

Row

Column

DQMn

Data

Activate

Read

First data out

CL = 2

CLK

ALE