Motorola MPC8260 User Manual
10-42
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part III. The Hardware Interface
should be set. Setting this bit causes the memory controller to add another cycle for each
address phase.
address phase.
Note that EAMUX can also be set in any case of delays on the address lines, such as address
buffers.
buffers.
Figure 10-26. EAMUX = 1
10.4.6.8 External Address and Command Buffers (BUFCMD)
In 60x-compatible mode, external buffers may be placed on the command strobes, except
CS, as well as the address lines. If the additional delay of the buffers is endangering the
device setup time, P/LSDMR[BUFCMD] should be set. Setting this bit causes the memory
controller to add one cycle for each SDRAM command.
CS, as well as the address lines. If the additional delay of the buffers is endangering the
device setup time, P/LSDMR[BUFCMD] should be set. Setting this bit causes the memory
controller to add one cycle for each SDRAM command.
Figure 10-27. BUFCMD = 1
10.4.7 SDRAM Interface Timing
The following Þgures show SDRAM timing for various types of accesses.
CLK
SDAMUX
CMD
MA[0Ð11]
Row
Column
NOP
Act
Read
NOP
NOP
Address setup cycle
ALE
CLK
SDAMUX
CMD strobes
MA[0Ð11]
Row
Column
Activate
Read
NOP
NOP
(without cs)
CS
ALE
Command setup cycle
Command setup cycle